Method of assigning chip I/O's to package channels

Details Method of assigning chip I/O's to package channels Method of assigning chip I/O's to package channels

2001-09-06

2003-12-09

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06662352

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the design of integrated circuit devices; more specifically, it relates to a method for selecting and assigning integrated circuit chip I/O's to package pins based on electrical properties of package channels.
2. Background of the Invention
The design of integrated circuit devices includes designing integrated circuit chips, designing chip packages and assigning I/O cells and power inputs to specific package pins. Generally, floor planning of the integrated circuit chips is performed after assignment of package pins to minimize signal delays to and from I/O cells and ensure adequate power distribution.
Historically a static timing analysis would be performed on the integrated circuit chip design to ensure that timing constraints were met. In modern design technique, static timing is based on determination of signal edge arrivals at the input of the I/O driver circuit and then in a separate simulation using a full netlist representation of the I/O driver and off-chip network, a determination of the delay from the input of the I/O driver circuit to the load on the network is performed. Such a simulation is very time consuming and only estimates the effect on timing of the package and other portions of the off-chip net. Further, package induced racing conditions are not accounted for. Of more concern, in the ASIC (application specific integrated circuit) environment, the simulation must be repeated for every chip/package combination.
A technique that would allow for characterization of a package in a manner that is applicable to different ASIC chips and accounted for actual delays in the package channels would save simulation time, reduce timing analysis failures which would require modifying the chip design and also increase the performance of the chip/package combination.
BRIEF SUMMARY OF THE INVENTION
Summary of the Invention
A first aspect of the present invention is a method of allowing a user to assign I/O cells of an integrated circuit chip to package channels of a package, comprising: calculating package RLC values for each package channel in the package; and assigning each I/O cell to one or more package channels based on the calculated package RLC values of the package channels.
A second aspect of the present invention is a computer system comprising a processor, an address/data bus coupled to said processor, and a computer-readable memory unit coupled to communicate with the processor, the memory unit containing instructions that when executed implement a method for allowing a user to assign I/O cells of an integrated circuit chip to package channels of a package, the method comprising the computer implemented steps of calculating package RLC values for each package channel in the package; and assigning each I/O cell to one or more package channels based on the calculated package RLC values of the package channels.


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