Method of assembly stress protection

Details Method of assembly stress protection Method of assembly stress protection

1999-11-01

2001-02-27

Picardàt, Kevin M. (Department: 2823)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Including contaminant removal or mitigation

C438S106000, C438S107000, C438S110000, C438S118000

Reexamination Certificate

active

06194249

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to the general field of integrated circuit packaging with particular reference to protection by molded plastic.
BACKGROUND OF THE INVENTION
In general, integrated circuits consist of a silicon wafer on whose upper surface have been formed a number of layers, the topmost of these including several alternating layers of metal and dielectric. For low-cost packaging, it is common practice to encapsulate the structure with a layer of molded plastic. This layer of plastic is applied directly onto the topmost metal wiring, a final layer of passivation dielectric being omitted as a cost saving measure.
It has been found that there are certain problems associated with this approach. One such problem is the so-called single broken long metal line problem in which lines of wiring that are isolated on the surface (no other wiring lines close by) are subject to destruction as a result of the application of the molding plastic (usually in the form of a jet carrying significant force). Another, more general, problem is that during thermal cycling, because of thermal stress due to mismatch between the plastic and the silicon, the possibility of delamination can arise.
Referring now to
FIG. 1
, we show, in schematic cross-section, a portion of a silicon wafer
10
in whose upper surface various components making up integrated circuits have been formed. The inter-metal dielectric layer
11
is seen on the surface of wafer
10
with two examples of the wiring (seen in cross-section) on its top surface, shown schematically as projections
12
. Covering the top surface of
11
as well as metallic wiring
12
, is layer
13
of molded plastic.
In
FIG. 2
we illustrate the two types of problem, discussed above, and their effect on the structures shown in FIG.
1
. As a result of stress due to thermal mismatch, plastic layer
13
has delaminated, as pointed to buy Arrow
21
, exposing the top surface of the structure to external contamination. Also seen is broken wire
24
which was damaged during the molding process and which (in this particular example) has been pulled away from the surface by the plastic.
One solution to the lone wire breakage problem that has been described in the prior art is the addition of extra dummy lines (unconnected to the main circuits) that help to reduce and distribute the force of the molding jet. While effective in the prevention of breakage, this solution makes a circuit susceptible to parasitic capacitor effects and is therefore undesirable from an electrical standpoint. Additionally, providing dummy lines, while reducing the probability of delamination during thermal cycling, will not always eliminate it, particularly if large uncovered areas on the surface of the final inter-metal dielectric layer still remain.
A routine search of the prior art was made but no solution to the above discussed problems similar to those of the present invention were encountered. Several references of interest were however found. For example, Bothra et al. (U.S. Pat. No. 5,618,757), as part of their process also formed dummy raised areas of oxide, but their process then goes on to fill the valleys with spin-on-glass as a way of planarizing, thereby teaching away from the present invention.
Nakano (U.S. Pat. No. 4,902,646) shows a method of forming dummy metal (as opposed to dielectric) patterns while Lee (U.S. Pat. No. 5,441,915) and Yang et al. (U.S. Pat. No. 5,798,298) both teach the dummy metal line process that we discussed above.
SUMMARY OF THE INVENTION
It has been an object of the present invention to provide a process and structure whereby low-cost packaging of an integrated circuit can be achieved.
Another object of the invention has been that the top layer of said packaged integrated circuit be of molded plastic.
A still further object of the invention has been that no damage be done to the upper-most wiring, particularly long single metal lines, during the molding process.
Yet another object of the invention has been that said molded plastic layer remain firmly adhering to the upper surface of the integrated circuit and not be subject to delamination as a result of thermal cycling.
These objects have been achieved by inter-posing a dummy layer of dielectric material between the upper surface of the integrated circuit wafer and the molded plastic layer. This dummy layer is patterned and etched so that its surface becomes an alternating series of valleys and ridges, care being taken to ensure that all wiring lines are protected by being inside ridges. This structure serves both to protect the wiring lines during the application of the molded plastic and, because of the large surface area of contact between plastic and integrated circuits, excellent adhesion of the molded plastic to the wafer is obtained.


REFERENCES:
patent: 4902646 (1990-02-01), Nakano
patent: 5441915 (1995-08-01), Lee
patent: 5618757 (1997-04-01), Bothra et al.
patent: 5763057 (1998-06-01), Sawada et al.
patent: 5798298 (1998-08-01), Yang et al.
patent: 5913110 (1999-06-01), Herbst
patent: 6043551 (2000-03-01), Seshan

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