Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-03-23
2001-05-08
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06230308
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a method of assembling modules to form a complex integrated circuit. The invention also relates to an integrated circuit and a module architecture of the stack type. The invention relates in particular, but not exclusively, to a method of assembling modules to form an integrated circuit, and the description which follows makes reference to this field of application for convenience of illustration.
BACKGROUND OF THE INVENTION
High-complexity integrated circuits, such as a microprocessor integrated in a single chip, for example, are known to include a plurality of sub-circuits, commonly termed modules, which are interfaced by suitable electrical connections carrying system signals. These signals may either be data or control signals which are transmitted under management by a supervisory module, such as a CPU.
Each of the modules included in a single integrated circuit is intended to implement a specific function. For example, certain modules may function as analog-to-digital converters, or serial circuits, or logic units, etc. An individual module contains an interface circuit enabling it to communicate with other modules.
FIG. 1
shows schematically a portion of a final integrated circuit CIF comprising four modules and being assembled in a conventional manner. In this example, the final integrated circuit CIF portion comprises first
1
, second
2
, third
3
and fourth
4
modules, respectively designated LOGICA
—
1, LOGICA
—
2, LOGICA
—
3 and LOGICA
—
4. These four modules have first IF
1
, second IF
2
, third IF
3
and fourth IF
4
interface circuits, respectively, which are respectively designated INTERFACCIA
—
1, INTERFACCIA
—
2, INTERFACCIA
—
3 and INTERFACCIA
—
4.
It should be noted that the modules in an integrated circuit may come in two general categories: simple modules, which are characterized by having a small number of transistors and a simple interface circuit (the modules
2
,
3
and
4
in the example of FIG.
1
); and complex modules, which are characterized by having a large number of transistors and either a simple or complex interface circuit (such as module
1
in the example of FIG.
1
).
When formed on a semiconductor, the layout of each of these modules, whether simple or complex, is usually given an aspect ratio, or length-to-width layout ratio, aimed at producing the densest possible integrated circuit. The different modules are then assembled, either manually or automatically, into the final integrated circuit CIF portion.
The schematic presentation of
FIG. 1
brings to light some limitations of this conventional assembly method, as specified below.
1. A high silicon area requirement, for interfacing the individual modules. The final integrated circuit CIF portion of
FIG. 1
includes a number of interface circuits equal to the number of modules, and a complicated pattern of buses
5
must be provided for supplying these interface circuits IF
1
, IF
2
, IF
3
and IF
4
.
2. An intensification of the capacitance driven from a common system bus
8
, connected to the complicated pattern of buses
5
and to additional connection buses
6
and
7
, resulting in the speed of the final integrated circuit CIF portion being slowed.
3. More complicated assembling of the individual modules
1
,
2
,
3
and
4
, resulting in lengthened times for developing the final integrated circuit CIF.
An alternative approach would be to make all modules, both simple and complex, with the same length, so as to simplify the assembling procedure. However, even this alternative approach has a serious drawback. In fact, the modules it produces would not be individually optimized, while a large area would be occupied by internal connections commonly known as the connection paths.
SUMMARY OF THE INVENTION
In view of the foregoing background, it is therefore an object of the present invention to provide a method of assembling modules into an integrated circuit, which has such structural and functional features as to overcome the limitations of prior assembling methods, especially with regard to the silicon area requirement.
The present invention is directed to creating module architectures aligned along one dimension, specifically architectures of simple modules having an individually optimized aspect ratio to produce a dense final integrated circuit, having the same width along a direction X, and being aligned in their length direction. Thus, a more efficient aspect ratio is obtained in the respect of both the individual simple modules and the final integrated circuit.
The present invention is also directed to a method as previously indicated of assembling modules to form a complex integrated circuit including a plurality of such modules, which method is characterized in that it provides a module architecture which is aligned along one dimension of the modules. The integrated circuit, comprising at least a plurality of modules, preferably comprises at least one portion constructed as a module architecture aligned along one dimension of the modules.
The module architecture, comprising a plurality of modules and being adapted for introduction into a complex integrated circuit, is characterized by the plurality of modules being aligned along one module dimension. The module architecture is further characterized in that it comprises a common interface circuit combining all the characteristics of individual interface circuits of the individual modules.
REFERENCES:
patent: 4926376 (1990-05-01), Rosini
patent: 5870310 (1999-02-01), Malladi
patent: 5915103 (1999-06-01), Chambers et al.
Lamore et al., “Layout Placement of Sliced Architecture, ” IEEE Transactions on Computer-Aided Design, vol. 11, No. 1 Jan. 1992, pp. 102-114.*
Paik et al., “Optimal Folding of Bit Sliced Stacks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, No. 11, Nov. 1993, pp. 1679-1685.
Battaia Alberto
Ganzelmi Roberto
Pozzi Cesare
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Galanthay Theodore E.
Garbowski Leigh Marie
SGS--Thomson Microelectronics S.r.l.
Smith Matthew
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