Method of assembling integrated circuits to a silicon board

Details Method of assembling integrated circuits to a silicon board Method of assembling integrated circuits to a silicon board

1990-12-17

1993-06-01

Arbes, Carl J.

Metal working

Method of mechanical manufacture

Electrical device making

29832, 26427213, H05K 334

Patent

active

052148440

ABSTRACT:
An assembly structure and process for attaching integrated circuits to multichip modules and attaching the module to a printed circuit board. An epoxy loaded with diamond dust or boron nitride is used to attach the integrated circuit to the module. The dust material increases the thermal conductance of the epoxy for improved heat dissipation without substantially increasing the capacitance of interconnect routed underneath the epoxy. Reverse wedge wire bonding is also used to electrically connect the integrated circuit to the module allowing greater chip densities on the module surface. The chip/module assembly can then be mounted on a printed circuit board and the module leads wired directly to the board.

REFERENCES:
patent: 4293587 (1981-10-01), Trueblood
patent: 4467400 (1984-08-01), Stopper
patent: 4471839 (1984-09-01), Chamberlain
patent: 4484215 (1984-11-01), Pappas
patent: 4486705 (1984-12-01), Stopper
patent: 4489397 (1984-12-01), Lee
patent: 4493055 (1985-01-01), Osman
patent: 4643804 (1987-02-01), Lynch et al.
patent: 4675717 (1987-06-01), Herrero et al.
patent: 4703288 (1987-10-01), Frye et al.
patent: 4732865 (1988-03-01), Evans et al.
patent: 4789645 (1988-12-01), Calviello et al.
patent: 4802532 (1989-02-01), Dawes et al.
patent: 4826896 (1989-05-01), Proctor
patent: 4914815 (1990-04-01), Takada et al.
patent: 4923825 (1990-05-01), Blouke et al.
patent: 4937653 (1990-06-01), Blonder et al.
patent: 4955132 (1990-09-01), Ozawa
Abstract of Japan Pat. 88-40698 by NEC Corp. entitled Seal Resin Contain Metal Powder; Useful Coating Hybrid IC.
Abstract of IEEE Trans. Compon., Hybrids, Manf. Technol., 1985, CHMT-8(4) 490-9 by M. Mahalingam et al.
Abstract of Pr. Nauk. Inst. Technol. Electron. Politech. Wroclaw. 1986, 34, 89-92 by W. Janke et al.
J. Electronic Materials, vol. No. 4, 1988, pp. 285-289, PT Wire Wedge Bonding: A New IC and Microsensor Interconnect by J. V. Mantese et al.
"Multichip Modules: Next Generation Packages", Robert R. Johnson, IEEE Spectrum, Mar. 1990.
"Forming Decoupling Capacitors On A Substrate", p. 1188, Sep. 1976, IBM Techincal Disclosure Bulletin.
"Multi-Chip Packaging Technology for VSLI-Based Systems", pp. 224 & 225, Feb. 30, 1987, IEEE 1987 Solid-State Circuits Conference.
Tuckerman, et al., "Ultrahigh Thermal Conductance Micro-Structures for Cooling Integrated Circuits" pp. 145-149, May 1982.
Tuckerman, "Heat-Transfer Microstructures for Integrated Circuits", Ph.D. Thesis, Stanford University, 1984.
Tuckerman, "High Performance Liquid Cooling of Integrated Circuits Using Silicon Microstructures", Bulletin of the American Physical Society, Ser. 2, V. 29, No. 3, pp. 463, 1984.
McWilliams et al., "Wafer-Scale Integration" Energy and Technology Review, pp. 1-9, 1985.
Mundinger, D. et al, "Demonstration of High-Performance Silicon Microchannel Heat Exchangers for Laser Diode Array Cooling" Sep. 19, 1988.
Wolfe, "Electronic Packaging Issues in the 1990s", Electronic Packaging & Production, Oct. 1990.
Bernhardt, et al., "Multichip Packaging for Very High Speed Digital Systems", Applied Surface Science, V. 46, 1990.
Low-Cost Multichip Modules Push Limits of Packaging, Malinak, Electronic Design Intl., Jul. 1990 by D. Maliniak.
Start-Up Developing Multichip RISC Modules, MicroDesign Resource Inc., 1990, Microprocessor Report, May 30, 1990, vol. 4, No. 10, May 30, 1990.
Fabrication of High Density Multichip Interconnect Substrates, Licari, et al, IEEE, 1989 Natl. Aerospace & Electronics Conf WAECON vol 4, pp. 1682-1688.
Interconnection and Packaging of Solid State Circuits, Pedder, IEEE, J. Solid State Circuits vol. 24, No. 3, Jun. 1989, pp. 698-703.
A 1-Mbit Full Wafer MOS RAM , Egawa, et al, IEEE, Trans. on Electron Devices Aug. 1980 vol. FD-27, No. 8, pp. 1612-1621.
Wafer-Chip Assembly for Large Scale Integration, Kraynak, IEEE, Trans. on Electron Devices vol. ED-15, No. 9, Sep. 1968, pp. 660-663.
Wafer-Scale Integration: the Limits of VLSI?, Peltzer, VLSI Design, Sep. 1983, pp. 43-47.
MMIC vs Hybrid: Glass Microwave ICs Rewrite the Rules, Perko, et al, Microwave Journal, Nov. 1988, pp. 67-76.
Multichip Assembly with Flipped Integrated Circuits, Heinen, et al, IEEE, Trans Components, Hybrids and Mfg. Tech. vol. 12, No. 4, Dec. 1989, pp. 650-657.
Chip Alignment Templates for Multichip Module Assembly, Tewksbury et al, IEEE Trans. on Components, Hybrids & Mfg. Tech. vol. CHMT-10, No. 1, Mar. 1987, pp. 111-121.
Ultra-Reliable Packaging for Silicon-on-Silicon WSI, Hagge, IEEE, Trans. on Components, Hybrids & Mfg. Tech. vol. 12, No. 2, Jun. 1989, pp. 170-177.
Thermal Module Design for Advanced Packaging, Hwang, et al, J. Electronic Materials vol. 16, No. 5, 1987, pp. 347-355.
A Technology for Optical Interconnections Based on Multichip Integration, Tsang et al, Optical Engineering, Oct. 1986, vol. 125, No. 10.
Low Stress Design of Flip Chip Technology for Si on Si Multichip Modules, Yamada, et al, IEPS, Oct. 1985, pp. 551-556.
New Packaging Strategy to Reduce System Costs, Balde, IEEE Intr. Conf on Computer Design: VLSI in Computers Oct. 1984, pp. 579-581.
A High Speed Multichip RAM Module with Thermal Stress Free Configuration, Satoh, et al, ICCD 1984, pp. 569-572.
Recent Developments in Silicon Hybrid Multichip Modiules, Corless, IEEE, Intr. Electronic Mfg. Technology Symposium Sep. 1989, pp. 111-117.
The Design of a Multichip Single Package Digital Signal Processing Module, Lin-Hendel, et al, IEEE 1989 Intr. Conf. on Computer Design: VLSI in Computers and Processors pp. 224-228.
Silicon Interconnect Technology, Johnson et al, Electronic Convention Mngmnt., Electro 87 Mini/Micro Northeast Conf. Record 1987, p. 36/1.
Discrete Wafer Scale Integration, Johnson, et al, IFIP, 1986.
Silicon on Silicon Packaging, Spielberger, et al, IEEE Trans. Components, Hybrids & Mfg. Technology, vol. CHMT-7, No. 2, Jun. 1984, pp. 193-196.
Silicon Packaging, A New Packaging Technique, Huang, et al, IEEE, Custom IC Conf. Rochester, N.Y. May 1983 pp. 142-146.
Multichip Thin-Film Technology on Silicon, Johnson, et al, IEEE, Trans. Components, Hybrids and Mfg. Technology vol. 72, No. 2, Jun. 1989, pp. 185-194.
Multichip Packaging Technology with Laser-Patterned Interconnect Barfknecht et al, IEEE, Trans. Components, Hybrids and Mfg. Tech. vol. 12, No. 4 Dec. 1989, pp. 646-649.
Multichip Modules AIM at Next-Generation VLSI, Lyman, Electronic Design, Mar. 1989, pp. 33-36.
Internal Thermal Resistance of a Multi-Chip Packaging Design for VLSI Based Systems, Lee, IEEE, Trans. Comp., Hybrids & Mfg. Tech. vol. 12, No. 2 Jun. 1989, pp. 163-169.
High Heat Flux Cooling for Silicon Hybrid Multichip Packaging, Jaeger, et al, IEEE, Trans. Components, Hybrids & Mfg. Tech. vol. 12, No. 4, Dec. 1989 p. 772.
New TCE-Matched Glass Ceramic Multichip Module: II Materials, Mechanical and Termal Aspects, Carrier, et al, IEEE 39 Electronics Computer Conferon May 1989.
Microelectronics Packaging II, Schwartz, Ceramic Bulletin, vol. 63, No. 4, 1984, pp. 577-581.
Applications of Thin Film Interconnection Technology for VLSI Multichip Packaging, Ting, et al, Proc. of 1987 Intr. Symposium on Microelectronics by Intr. Soc. Hybrid Microelectronics Sep. 1987.

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