Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2001-10-18
2004-07-06
Bataille, Pierre (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S158000, C710S264000, C710S240000
Reexamination Certificate
active
06760820
ABSTRACT:
RELATED APPLICATION(S)
Not applicable
FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
TECHNICAL FIELD
This invention relates to buffer memory access management within a disk drive data storage device and more particularly to a head servo interrupt system for improving microprocessor channel priority during memory access arbitration in a single processor, shared memory disk drive embedded controller environment.
BACKGROUND OF THE INVENTION
Prior disk drives have included, in addition to a disk data channel and a host data channel, at least one embedded digital microprocessor for controlling various functions of the disk drive such as head positioning, spindle motor speed regulation, read channel adjustments for zoned data recording and error correction tasks, and the supervision of data block transfers between disk and host in response to host commands received via the host channel. Such disk drives have typically included a large data cache memory for temporary storage of multiple data blocks in transit between the disk data storage surface and the host computing system, and smaller first-in-first-out (“FIFO”) buffers associated with the disk data channel and the host data channel.
More recently, use of on-board shared buffer memory has been employed to provide storage of instructions and data needed for microprocessor operations, with microprocessor accesses to buffer memory being multiplexed between disk channel and host channel block transfer memory accesses. These relatively large shared memory arrays have typically employed dynamic random access memory chips (DRAM).
The DRAM memory in disk drive systems must be shared among several processes, often referred to as “clients.” This sharing arrangement presents an interesting challenge to the disk drive designer. On the one hand, a DRAM operates most efficiently if the same client presents a continuous series of sequential access requests to the DRAM in page mode. Depending upon DRAM type, page mode accesses are from three to nine times faster than non-page mode access requests. However, each client typically needs to obtain DRAM access as often as possible, which reduces the time a particular access can be handled in page mode.
In some prior disk drives, the various process and resource clients have accessed DRAM by employing multiplexing and access arbitration. For example, if only one client, such as the disk data channel, has frequent, high-bandwidth, “absolutely must have” need for DRAM access, a simple priority technique suffices. The disk data channel typically has this requirement, and because the length of the disk FIFO is limited, data will be lost if the disk data channel FIPO is overrun. Other high-bandwidth channels, such as the host interface (SCSI or ATA), can be throttled when its FIFO is full. Therefore, it is desirable to give the disk channel the highest priority when its FIFO is nearly full, and hold the priority high until the FIFO is empty.
On the other hand, the host channel may have access gaps. Therefore it has a lower priority, but when it obtains access to the DRAM, it maintains its access until its FIFO is emptied, or until the disk channel overrides. The microprocessor, memory refresh, and other clients may be assigned a medium priority.
One example of such a technique is described in U.S. Pat. No. 5,465,343 for SHARED MEMORY ARRAY FOR DATA BLOCK AND CONTROL PROGRAM STORAGE IN DISK DRIVE, which is assigned to the assignee of this application, and is incorporated herein by reference. In this approach, buffer memory access arbitration follows a hierarchical approach with each internal client seeking buffer access at a predefined priority. For example, the disk data channel has the highest priority because data transfers to and from the disk must be made in synchronism with storage disk rotation to avoid delays caused by multiple disk rotation latencies during a data transfer. DRAM memory refresh is accorded a next priority level, and host interface or control microprocessor clients are accorded yet a lower priority level.
Round-robin access techniques are described in which when all channels are requesting DRAM access, each channel is serviced in a fixed order and for a predetermined maximum time interval. If any channel is not requesting access, the next channel in the priority sequence assumes access, and so on. In any of these access techniques, the DRAM is never idle if an unserviced access request exists from any channel.
A problem with this round robin access technique is that all the predetermined time intervals must account for the worst case access times. Another problem is that some clients have dissimilar DRAM data access patterns. For example, the disk and host channels employ large sequential block accesses to the DRAM via multi-word FIFOs and are, therefore, suited for fast, page mode transfers. In contrast, the microprocessor typically fetches and decodes single instructions from the buffer, thereby potentially delaying subsequent buffer memory accesses by the microprocessor.
These problems manifest themselves as a memory access uncertainty time that ranges from practically zero to the above-described predetermined maximum time interval, which must always be accommodated. This not only reduces the DRAM access time, but also reduces the time available for the execution of high-priority head seeking and tracking routines that are critical to overall disk drive performance. Such routines typically require at least half of the total available microprocessor time, with the reduced time compromising the head servo phase margin and increasing timing jitter in the head servo loop.
It is also known in the digital computer field to provide blended priority and round-robin bus arbitration techniques. While such techniques may work well within multiprocessor and multimedia computing environments, they are not adapted to the unique problems and challenges of shared buffer management in a low-cost hard disk drive.
What is needed, therefore, are further improvements in the techniques for accessing buffer memory in an embedded disk drive controller employing a shared memory and a single microprocessor.
SUMMARY OF THE INVENTION
An object of this invention is, therefore, to provide an apparatus and a method for efficiently and effectively arbitrating among competing clients seeking access to a shared memory array within the embedded controller of a hard disk drive in a manner overcoming limitations and drawbacks of the prior art.
Another object of this invention is to employ a head servo-process interrupt signal in combination with a circular priority queuing structure to reduce the access time of clients contending for access to a single buffer memory array within a disk drive.
Yet another object of this invention is to employ a head servo-process interrupt signal in combination with a circular priority queuing structure to increase the head servo processing time available, thereby reducing uncertainty time jitter while improving disk drive phase margin, seeking, and tracking performance.
A single microprocessor hard disk drive having a shared buffer memory for storing sector data as well as microprocessor variables and code includes a buffer memory arbitrator for arbitrating requests from various channels or clients for access to the shared buffer memory. The arbitrator arranges various channels including a disk data channel, a host interface data channel, and a microprocessor channel into a round-robin circular priority queue, with the disk data channel normally assigned the highest priority for buffer access. A state machine carries out the arbitration cycle by sequentially servicing access requests pending within the queue. The state machine also senses a servo interrupt to elevate the priority of any pending microprocessor access requests to the shared buffer, such that the accesses clear rapidly, thereby allowing the servo interrupt servicing routine to process more rapidly and completely. The servo interrupt is preferably asserted during a spoke gate, or wedge, time when the data tr
Henson James A.
Kahlert Gregory R.
Uppuluri Minnie T.
Bataille Pierre
Maxtor Corporation
Sigmond David M.
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