Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-04-25
2006-04-25
Knight, Anthony (Department: 2121)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C709S238000, C716S030000, C716S030000, C716S030000, C710S056000, C713S153000
Reexamination Certificate
active
07036104
ABSTRACT:
A method of and system for optimizing a tree to meet timing constraints inserts buffers at selected ones of the internal nodes of a tree to form a plurality of subtrees. The method sizes the wires of the subtrees according to a wire code for each subtree, wherein each wire of a subtree has the same wire code. The buffers are inserted and the wires are sized such that slack along the path from a single source node to each sink node of the tree is equal to or greater than zero.
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Alpert Charles Jay
Devgan Anirudh
Quay Steven Thomas
Dillon & Yudell LLP
International Business Machines - Corporation
Knight Anthony
Salys Casimer K.
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