Method of and circuitry for generating staggered restore timing

Details Method of and circuitry for generating staggered restore timing Method of and circuitry for generating staggered restore timing

1988-01-15

1989-05-23

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Differential sensing

365203, 36518908, G11C 700

Patent

active

048336548

ABSTRACT:
A memory cell array is divided into four blocks. A sense amplifier and a restore circuit and provided in each of the blocks. The sense amplifier operates by a sense amplifier driving signal and the restore circuit operates by a restore circuit driving signal. A driving signal generating circuit generates two restore circuit driving signals at different timing. In order to generate the restore circuit driving signals, a block selecting signal, a block non-selecting signal, a sense amplifier driving signal and two dummy bit lines are used. Restoring operation in a block selected by the block selecting signal and restoring operation in a non-selected block are performed at different timing by the above described restore circuit driving signals.

REFERENCES:
patent: 4734890 (1988-03-01), Miyatake et al.
patent: 4736343 (1988-04-01), Hidaka et al.
R. A. Kertis et al., "A 60ns 256K.times.l Bit DRAM Using LD Technology and Double-Level Metal Interconnection", IEEE Journal of Solid-State Circuits, vol. SC-19, No. 5, Oct., 1984, pp. 585-590.
R. A. Kertis et al., "A 59ns 256K DRAM Using LD Technology and Double Level Metal", 1984, IEEE International Solid-State Circuits Conference, Feb. 22, 1984.

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