Method of and circuit for verifying a layout of an...

Details Method of and circuit for verifying a layout of an... Method of and circuit for verifying a layout of an...

2006-08-11

2008-12-09

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C703S013000, C703S014000

Reexamination Certificate

active

07464350

ABSTRACT:
A method of verifying a layout of an integrated circuit device is disclosed. The method comprises steps of receiving a physical layout for a schematic of a circuit implemented in the integrated circuit device; generating an implant table file having data showing a relationship between layers and device types of the integrated circuit device; and generating a layout-versus-schematic rules file using the implant table file.

REFERENCES:
patent: 5062054 (1991-10-01), Kawakami et al.
patent: 5901066 (1999-05-01), Hong
patent: 7096441 (2006-08-01), Lo et al.
patent: 7124382 (2006-10-01), Eccles et al.
patent: 2005/0223347 (2005-10-01), Okuaki

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