Method of and circuit for enabling variable latency data...

Details Method of and circuit for enabling variable latency data... Method of and circuit for enabling variable latency data...

2004-09-15

2009-11-24

Tsai, Henry W. H. (Department: 2184)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output process timing

C711S167000

Reexamination Certificate

active

07624209

ABSTRACT:
A method of enabling variable latency data transfers in an electronic device, such as an FPGA with an embedded processor, is described. According to one aspect of the invention, a method comprises steps of providing an address for a data transfer between a memory controller and a peripheral device; coupling an address valid signal to the peripheral device; transferring the data between the memory controller and the peripheral device; and receiving a data transfer complete signal at the memory controller. According to another aspect of the invention, an integrated circuit enabling a variable latency data transfer is described. The integrated circuit comprises peripheral device; a memory controller coupled to the peripheral device; an address valid signal coupled from the memory controller to the peripheral device; and a transfer complete signal coupled from the peripheral device to the memory controller.

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