Method of and circuit for buffering data

Details Method of and circuit for buffering data Method of and circuit for buffering data

2006-09-27

2010-02-23

Bataille, Pierre-Michel (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C708S404000

Reexamination Certificate

active

07669017

ABSTRACT:
A method of buffering data in a circuit processing data in both a natural address order and a modified address order is described. The method comprises the steps of storing a first block of data according to a first addressing order of a natural address order or a modified address order; reading the first block of data stored in a buffer according to the other addressing order of the natural address order and the modified address order; and simultaneously writing a second block of data to the buffer in the other addressing order while reading the first block of data stored in a buffer according to the other addressing order.

REFERENCES:
patent: 6430587 (2002-08-01), Orling
patent: 6687315 (2004-02-01), Keevill et al.
patent: 7415584 (2008-08-01), Gibb et al.
Newton, H., Newton's Telecom Dictionary, 19th Edition, CMP Books, 2003; p. 638 “Programmable Logic”.

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