Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1998-04-03
2000-10-31
Iqbal, Nadeem
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
365201, G06F 1100
Patent
active
06141767&
ABSTRACT:
A graphical user interface is used to display contents of a configuration memory and includes a hierarchical window illustrating directories and entries within the configuration memory including the relationships between the directories and entries and a data window for displaying data stored within the configuration memory and signalling errors corresponding to the data. The errors are determined by processing the data being displayed to determine a reference value for each entry within the data and to determine if any offset value, pointer value and count value included within any entry references a memory location outside of a boundary of the memory. The reference value specifies a number of times each entry is referenced. Errors are signalled within the data window by displaying entries corresponding to errors in a first color and entries which do not include errors in a second color. The system further includes a bus structure node circuit for coupling the system to other devices over a bus structure. Appropriate headings of directories and entries are displayed with the data in the data window. The bus structure is preferably an IEEE 1394-1995 serial bus.
REFERENCES:
patent: 4238852 (1980-12-01), Iga et al.
patent: 4726028 (1988-02-01), Himeno
patent: 4788684 (1988-11-01), Kawaguchi et al.
patent: 4881232 (1989-11-01), Sako et al.
patent: 4910736 (1990-03-01), Tanaka et al.
patent: 5001714 (1991-03-01), Stark et al.
patent: 5020011 (1991-05-01), Stark et al.
patent: 5517508 (1996-05-01), Scott
patent: 5577219 (1996-11-01), Timko et al.
patent: 5627955 (1997-05-01), Gnirss et al.
patent: 5644709 (1997-07-01), Austin
patent: 5675540 (1997-10-01), Roohparvar
patent: 5815509 (1998-09-01), Deng et al.
IEEE, "1394-1995 Standard for a High Performance Serial Bus," 1995, USA.
ISO/IEC 13213:1994, ANSI/IEEE Std 1212 Cl. 8, 1994, pp. 79-100, USA.
Hu Qi
Shima Hisato
Iqbal Nadeem
Sony Corporation
Sony Electronics Inc.
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