Method of and apparatus for validating data read out of a multi

Details Method of and apparatus for validating data read out of a multi Method of and apparatus for validating data read out of a multi

1998-03-10

2000-07-04

Peikari, Behzad James

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711117, 710 56, G06F 1200, G06F 1300

Patent

active

060852909

ABSTRACT:
An apparatus for and method of enhancing the performance of a multi-port internal cached DRAM (AMPIC DRAM) by providing an internal method of data validation within the AMPIC memories themselves to guarantee that only valid requested data is returned from them, or properly marked invalid data. A modified technique for identifying bad data that has been read out of AMPIC memory devices in the system.

REFERENCES:
patent: 3832684 (1974-08-01), Besenfelder
patent: 3872431 (1975-03-01), Besenfelder et al.
patent: 5142541 (1992-08-01), Kim et al.
patent: 5490112 (1996-02-01), Hush et al.
patent: 5799209 (1998-08-01), Chatter
patent: 5835941 (1998-11-01), Pawlowski

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