Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
1996-12-16
2001-08-21
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S015000, C712S028000, C709S241000, C709S201000, C710S071000
Reexamination Certificate
active
06279098
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to multi-processor systems and more particularly relates to multiple-processor systems which utilize partitioning schemes.
2. Description of the Prior Art
Ever increasing demand for high throughput data processing systems has caused computer designers to develop sophisticated multi-processor designs. Initially, additional processors were provided to improve the overall bandwidth of the system. While the additional processors provided some level of increased performance, it became evident that further improvements were necessary particularly in the area system partitioning. Improved system partitioning schemes were necessary to optimize the parallel nature of such systems and to efficiently manage the growing number of processors included therein.
Partitioning of a system refers to the allocation of the system's data processing resources to a number of predefined “partitions”. Each partition may operate independently from the other partitions in the system. That is, partitioning may allow a number of parallel tasks to be independently executed within the system. For example, a first portion of the system resources may be allocated to a first partition to process a first task while a second portion of the system resources may be allocated to a second partition to process a second task.
A system controller may control the addition or deletion of the system resources to or from the various partitions in the system. That is, the system resources that are allocated to a particular partition may be added or deleted therefrom depending on the type of task performed by that partition. For example, a large task may require more system resources than a small task. A system controller may add resources to the partition of the system servicing the large task, and may delete resources from a partition servicing a smaller task, thereby increasing the efficiency of the overall system.
A major step in dynamic resource allocation was to provide input/output subchannels with the capability of dynamic allocation as taught in U.S. Pat. No. 4,437,157, issued to Witalka et al. Logical file designations for peripheral devices is suggested by U.S. Pat. No. 5,014,197, issued to Wolf. Similarly, U.S. Pat. No. 4,979,107, issued to Advani et al., suggests logical assignment of peripheral subsystem operating parameters.
The capability to reconfigure has been used in a number of systems applications, U.S. Pat. No. 4,070,704, issued to Calle et al., provides a boot strap program with the capability to change the initial load peripheral device upon determination of a failure in the primary loading channel. Perhaps the most often stated purpose for reconfiguration is to provide some degree of fault tolerance. U.S. Pat. No. 4,891,810, issued to de Corlieu et al., and U.S. Pat. No. 4,868,818, issued to Madan et al., suggest system reconfiguration for that reason. A related but not identical purpose is found in U.S. Pat. No. 4,888,771, issued to Benignus et al., which reconfigures for testing and maintenance.
The capability to reconfigure a data processing system can support centralized system control as found in U.S. Pat. No. 4,995,035, issued to Cole, et al. A current approach is through the assignment of logical names for resources as found in U.S. Pat. No. 4,245,306, issued to Besemer et al. and U.S. Pat. No. 5,125,081, issued to Chiba. An extension of the capability to identify resources by logical names is a virtual system in which the user need not be concerned with physical device limitations, such as suggested in U.S. Pat. No. 5,113,522, issued to Dinwiddie, Jr. et al.
In many systems, the system controller maintains overall control over the partitioning of the system. Thus, the system controller is typically in communication with each of the partitions within the system. For example, the system controller may provide each of the partitions with a number of partitioning bits, indicating which of the data processing resources are available for use thereby. Both processors and storage structures may be the subject of system partitioning. That is, a number of processors within the system may be allocated to a first partition while the remaining processors may be allocated to a second partition. Similarly, a number of storage structures may be allocated to the first partition while the remaining storage structures may be allocated to the second partition.
To support dynamic partitioning, or partitioning on-the-fly, each of the partitions within the system are often in communication with all other partitions. That is, each partition may dynamically transmit it's partitioning information to all other partitions within the system, thereby indicating which resources are associated therewith. Further, each partition may make dynamic requests for additional resources from the other partitions. Finally, each partition may be in communication with each of the data processing resources associated therewith. All of these control signals are typically provided using a parallel bus type interface.
Using a parallel bus type interface to transmit and receive the partition information between partitions, and between the partitions and the associated data processing resources, may consume a relatively large number of I/O pins on a corresponding ASIC (Application Specific Integrated Circuit), and a relatively large number of PC board traces. It is known that as technology progresses to larger scale integration, the number of I/O pins that are available on an ASIC may not grow proportionately with the logic space available on the component. Thus, the I/O pins have become a valuable resource. Further, it is known that the failure rate of the I/O pins on an ASIC is higher than the failure rate of the logic used to transmit the information. Finally, the number of PC board traces required for a particular design often limits the size of the corresponding PC board. It can readily be seen that using a parallel bus type interface to transmit and receive partition information may increase the number of I/O pins required, reduce the reliability of the partitioning mechanism, and may increase the overall size of a corresponding PC board design.
SUMMARY OF THE INVENTION
The present invention overcomes many of the limitations found in the prior art by providing a method and apparatus for serially transmitting partitioning information between system partitions, and between system partitions and the corresponding data processing resources. Serial transmission may allow the partitioning information to be transmitted using a single I/O ASIC pin, and a single trace on each PC board. In addition to reducing the required number of I/O ASIC pins and PC board traces, the present invention may increase the overall reliability of the partitioning mechanism.
In a preferred embodiment of the present invention, each of the partitions may be controlled by a partition controller. Each of the partition controllers may be in communication with a maintenance processor (i.e. support processor) as described above. To support the serial transmission of the partition information, the present invention contemplated providing a first serial interface coupling a first one of the partition controllers with a second one of the partition controllers, such that partitioning information may be serially transmitted from the second partition controller to the first partition controller via the first serial interface. A second serial interface may be provided between the first one of the partition controllers and the second one of the partition controllers, such that partitioning information may be serially transmitted from the first partition controller to the second partition controller via the second serial interface. Alternatively, it is contemplated that a single serial interface may be provided between the first and second one of the partition controllers, wherein the single interface may provide two-way serial communication therebetween using a time-division-mu
Bauman Mitchell A.
Boone Lewis A.
Schroeder Donald E.
Chan Eddie
Johnson Charles A.
Nawrocki, Rooney & Sivertson P.A.
Nguyen Dzung C.
Starr Mark T.
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