Static information storage and retrieval – Read/write circuit – Including specified plural element logic arrangement
Patent
1988-07-22
1990-06-12
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Including specified plural element logic arrangement
365193, 365194, 365226, 3072723, G11C 700, G11C 1140
Patent
active
049339028
ABSTRACT:
A clock generator circuit of a dynamic random access memory (RAM) comprises a power-on reset circuit and an NOR gate conneced to a row address strobe (RAS) terminal and the reset circuit. In operation, the power-on reset circuit generates a one-shot pulse immediately after the power supply is turned on. During a period of a pulse width of the one-shot pulse, this clock generator circuit operates as if it receives a high-level row address strobe (RAS) signal and, as a result, it is possible to reduce an excessive current flowing into the dynamic random access memory (RAM) at the time of turning on the power supply.
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Miyamoto Hiroshi
Yamada Michihiro
Bowler Alyssa H.
Hecker Stuart N.
Mitsubishi Denki & Kabushiki Kaisha
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