Adhesive bonding and miscellaneous chemical manufacture – Delaminating processes adapted for specified product – Delaminating in preparation for post processing recycling step
Patent
1993-02-01
1995-03-21
Hearn, Brian E.
Adhesive bonding and miscellaneous chemical manufacture
Delaminating processes adapted for specified product
Delaminating in preparation for post processing recycling step
437228, 156636, H01L 21306
Patent
active
053992334
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
This invention relates to a semiconductor substrate having a SOI (silicon on insulator) structure and, more particularly, to a method of polishing one of two silicon wafers attached to each other through an insulation layer so that the polished silicon wafer is formed as a thin layer having a uniform thickness of about 1 .mu.m or less.
BACKGROUND ART
With the increase in the density of packaging of semiconductor integrated circuits (ICs), the development of practical SOI substrates is being promoted. It is anticipated that SOI substrates will be used as an effective means for avoiding an increase in parasitic capacitance of transistors in high density ICs and occurrence of a latch-up phenomenon or the like in CMOS transistors.
In one method for manufacturing SOI substrates, two silicon wafers are attached with an SiO.sub.2 layer interposed therebetween, and in which one of the two silicon wafers is polished so that the thickness thereof is reduced to a predetermined value. If an ordinary polishing machine is used for this polishing, it is impossible to avoid the occurrence of non-uniformity in the reduced thickness of the polished silicon wafer to an extent of 1 .mu.m or more in terms of total thickness variation (TTV), However, to realize desired device characteristics, in particular, a high-speed operation of a MOS FET, a substrate in which the thickness of a silicon layer is 0.1 to 1 .mu.m is required. Further, with respect to SOI substrates for integrated circuits formed of fine CMOS elements having a channel length of 1 .mu.m or less, a thin silicon layer having a thickness of, for example, 0.05 .mu.m (500 .ANG.) is required. Therefore, it is impossible for existing polishing machines to uniformly reduce the thickness of the whole of a silicon wafer having a diameter of, for example, 6 inches.
As methods for solving such problems relating to the accuracy of polishing machines, various methods have been proposed in which a stopper formed of a material more difficult to polish in comparison with silicon and having a predetermined thickness is formed in a silicon layer previously reduced in thickness to several microns, and in which the final thickness is controlled with such a stopper. This kind of method utilizes the difference between polishing speeds, for examples, of silicon and silicon oxide and is called selective polishing.
A stopper formed of a SiO.sub.2 layer having a thickness of 0.1 .mu.m or less, for example, is embedded around chip regions or device formation regions defined in a silicon layer to be reduced in thickness to several microns. The silicon layer is polished so that the same thickness as that of the stopper. (Methods of this type are disclosed in Japanese Patent Laid-Open Publication Nos. 1-136328, 2-237066, 3-104224, and 3-108356).
FIG. 4 is a schematic cross-sectional view of an example of the above-described method. A silicon wafer 1 attached to another silicon wafer 2 forming a supporting substrate with an SiO.sub.2 layer 3 interposed therebetween is previously formed as a thin layer having a thickness of 3 to 4 .mu.m, and a stopper 4 is formed of an SiO.sub.2 layer in regions where no devices will be formed.
The silicon wafer 2 is fixed on a polishing jig 5 and is rotated on a rotating shaft 5A while being pressed against an upper surface of a surface table 6. A piece of polishing cloth 7 formed of, for example, polyurethane in which a silica sand powder is mixed is attached to the upper surface of the surface table 6. In this state, an abrasive is supplied to the upper surface of the surface table 6 to polish the silicon wafer 1 until the stopper 4 is exposed. In this manner, the silicon wafer 1 is polished and formed into a thin layer having a thickness of 1 .mu.m corresponding to that of the stopper 4.
However, if the silicon wafer 1 and the surface table 6 are not parallel to each other, the silicon wafer 1 is not polished uniformly and a state is exhibited in which the stopper 4 is exposed in a portion of the silicon wafer 1 so that the polishing spe
REFERENCES:
patent: 4735679 (1988-04-01), Lasky
patent: 4879258 (1989-11-01), Fisher
patent: 5081796 (1992-01-01), Schultz
W. J. Patrick et al., "Application of Chemical Mechanical Polishing to the Fabrication of VLSI Circuit Interconnections", J. Electrochem. Soc., vol. 138, No. 6, Jun. 1991, pp. 1778-1784.
Translation of Miyajima JP 3-108356.
Translation of Usui Shoji et al. JP 3-145129.
Translation of Nemoto et al. JP 2-257629.
Translation of Arimoto JP 2-237066.
Translation of Ogawa JP 62-199354.
"A Computer Controlled Polishing System for Silicon-on-Insulator (SOI)", Yamada et al, 5th International Workshop on Future Electron Devices-Three Dimensional Integration-(FED 3D Workshop), May 30-Jun. 1, 1988, Miyagi-Zao, pp. 201-205.
Arimoto Yoshihiro
Fukuroda Atsushi
Murazumi Maki
Fujitsu Limited
Gurley Lynne A.
Hearn Brian E.
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