Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1979-12-31
1982-08-10
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Bad bit
365201, 371 24, G11C 1140
Patent
active
043441556
ABSTRACT:
A memory matrix is divided into a plurality of zones, one of which has a predetermined address and is set aside for a control character having multiple bits, stored in plural cells of the one zone. Each cell stores electric charge, with the cells in the control zone storing a charge no greater than that in the remaining zones. After the cells of the control zone have been initially supplied with the predetermined control character, the cells of the control zone are isolated from write command signals during normal operation. The cells of the control zone can be read out during normal operation.
REFERENCES:
patent: 3518413 (1970-06-01), Holtey
patent: 3940601 (1976-02-01), Henry et al.
patent: 4034194 (1977-07-01), Thomas et al.
patent: 4047163 (1977-09-01), Choate et al.
Compagnie Internationale pour l'Informatique -CII-Honeywell Bull
Fears Terrell W.
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