Method of and apparatus for correcting edge placement errors in

Details Method of and apparatus for correcting edge placement errors in Method of and apparatus for correcting edge placement errors in

1992-10-23

1995-04-11

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

331 10, 371 1, 327159, 327175, H03D 324

Patent

active

054065909

ABSTRACT:
A method of starting up a system clock that has been generated by a phase-locked loop and correcting edge placement errors during coasting periods of the phase locked loop, and circuitry for accomplishing those methods. A low frequency master clock signal is distributed to circuits that generate high frequency local clock signals. These circuits generate the high frequency local clock signals using phase-locked loops in a frequency multiplier configuration. Lock indicator circuitry determines when the phase-locked loop has locked onto the master clock signal and then enables output buffers that then provide the high frequency clock signals to components in the system which need those local clocks. An intermediate frequency signal is fed back to the input of the voltage controlled oscillator in the phase locked loop to correct edge placement errors. A slightly earlier or leading version of the signal is used to correct cycle length variations without inducing duty cycle variations.

REFERENCES:
patent: 5027087 (1991-06-01), Rottinghaus
patent: 5144260 (1992-09-01), Stribling et al.
patent: 5193013 (1993-03-01), Swanberg
patent: 5254958 (1993-10-01), Flach et al.

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