Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-08-31
2001-06-05
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06243852
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of and all apparatus for logic circuit synthesis for automatically synthesizing a logic circuit according to a description of the logic circuit using a HDL (High-level Design Language) and a recording medium wherein a program for a computer performing the logic circuit synthesis according to the method is recorded.
As one of prior arts of the logic circuit synthesis, there is known a method disclosed in “BooleDozer: Logic synthesis for ASICs” by L. Stok et al., IBM J. RES. DEVELOP., VOL. 49, NO. 4, pp. 407-430 (July 1996).
FIG. 11
is a block diagram schematically illustrating a structural flow of the above prior art.
Referring to
FIG. 11
, the prior art apparatus comprises a compiler section
104
, a technology-independent optimization section
105
, a technology mapping section
106
, a timing optimization section
107
, a logic circuit output section
108
, a semiconductor library
103
and an inner database
102
used by the above sections.
The compiler section
104
compiles a HDL description
101
into a logical network composed of logical blocks including equation blocks, functional blocks such as adders and multiplexers, and primitive gates. The logical network is stored in the inner database
102
.
The technology-independent optimization section
105
performs technology-independent optimization of the logical network. Here, the technology-independent optimization means optimization not considering concrete hardware configurations of the logical blocks. In this prior art example, optimization methods such as so-called the constant propagation, the redundancy removal, the global flow analysis, the transduction, the cube factoring, and the kernel factoring are applied for the technology-independent optimization.
Then, referring to the semiconductor library
103
, the technology mapping section
106
generates a hardware network by assigning a matching hardware unit to each of the logical blocks of the logical network after processed through the technology-independent optimization section
105
. The hardware network is stored in the inner database
102
.
The timing optimization section
107
performs optimization of the hardware network referring to the semiconductor library
103
, making use of optimization methods such as so-called the fan-out correction, the fan-in reordering, the decomposition, and the inverter motion.
Finally, the logic circuit output section
108
generates a logic circuit
111
to be output referring to the semiconductor library
103
according to the hardware network after processed through the timing optimization section
107
.
Thus, a logic circuit is synthesized according to a HDL description in the prior art example.
However, in the conventional logic circuit synthesis such as above described, there has been a problem that one-to-one correspondences are not all retained between the HDL description and the logic circuit synthesized according thereto. This is because part of the information in the HDL description disappears in the process of the optimization.
For example, following logic in the HDL description;
S=(A and C) or (A and D) or (B and C) or (B and D),
P=(A and S), and
Q=(B and S),
is transformed, as the result of optimization according to the transduction, into another logic as follows;
S′=(C or D)
P=(A and S′), and
Q=(B and S′).
Thus, all intermediate signal S=(A and C) or (A and D) or (B and C) or (B and D) defined in the HDL description
101
is replaced with different intermediate signal S′=(C or D) in the synthesized logic circuit
111
, according to the prior art logic circuit synthesis. Here, the intermediate signal means a signal other than input/output signals of a logic circuit itself designed with a HDL module or output signals of sequential hardware units such as a flip-flop in the logic circuit. Similar omissions or deformations occur through the other optimization methods than the transduction.
When a logic circuit is sufficient to be once synthesized simply, the correspondence between the logic circuit and the HDL description may not be necessary to be referred to.
However, in most cases, the synthesized logic circuit should be checked as to whether it functions correctly as intended by the designer making use of detailed simulation, for example, even if the logic circuit is correctly synthesized according to a HDL description. This is because the logic circuit synthesis cannot check for a the desiginer's intention itself even if it can check logical inconsistency in the HDL description. Further, the designer may intend to revise the HDL description for improving performance of the synthesized logic circuit concerning a critical path thereof.
In these cases, it is difficult for the designer to correctly search corresponding parts of the HDL description when information of the intermediate signals is omitted or deformed automatically through the optimization.
When no optimization is applied, the above problem does not occur, of course, but performance (in area, delay and power) of the synthesized logic circuit would be too degraded.
SUMMARY OF THE INVENTION
Therefore, a primary object of the present invention is to provide a method of and an apparatus for logic circuit synthesis wherein a point, whereto each of intermediate signals defined in a HDL description corresponds, can be easily discriminated in a logic circuit synthesized from the HDL description, for enabling a designer to perform analysis, logical checks and revisions of the synthesized logic circuit easily and efficiently.
Another object of the present invention is to provide a method of and an apparatus for logic circuit synthesis wherein boundary information of unnecessary intermediate signals in the HDL description is allowed to be omitted, when priority is to be given to optimization performance in the logic circuit synthesis. Still another object of the invention is to provide a recording medium wherein a program for a computer performing the logic circuit synthesis according to the above inventions is recorded.
In order to achieve the object, a method of logic circuit synthesis for automatically synthesizing a logic circuit according to a description of the logic circuit using a HDL comprises steps of:
generating a logic circuit according to a HDL description always retaining boundary information concerning necessary intermediate signals defined in the HDL description; and
outputting a correspondence list describing information of each respective point of the logic circuit corresponding to each of the necessary intermediate signals, by editing the boundary information.
The necessary intermediate signals may be all intermediate signals defined in the HDL description, or may be variable intermediate signals defined in the HDL description and referred to by more than a predetermined number of nodes of the logic circuit.
Therefore, any point in the logic circuit, whereto the intermediate signals corresponds, can be easily discriminated, and the designer can easily and efficiently perform analysis, logical checks and revisions of the synthesized logic circuit referring to the correspondence list.
Further, when priority is to be given to optimization performance, boundary information of unnecessary intermediate signals is allowed to be omitted, in the logic circuit synthesis according to the invention.
Describing more concretely, the method of logic circuit synthesis according to the invention comprises steps of:
compiling a HDL description into a logical network, wherein boundary information concerning intermediate signals defiled in the HDL description is included;
performing technology-independent optimization of the logical network retaining the boundary information;
transforming the logical network into a hardware network retaining the boundary information, by assigning a matching hardware unit in a semiconductor library to each of logical blocks of the logical network after performing the technolog
Foley & Lardner
Kik Phallaka
NEC Corporation
Smith Matthew
LandOfFree
Method of and an apparatus for logic circuit synthesis does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of and an apparatus for logic circuit synthesis, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of and an apparatus for logic circuit synthesis will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2524964