Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-06-12
2004-02-17
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C714S724000
Reexamination Certificate
active
06694495
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to testing integrated circuits for potential fabrication faults. More specifically, the present invention relates to a method of selecting test vectors for use in static current testing of integrated circuits having embedded memory devices.
BACKGROUND OF THE INVENTION
Static current testing has been used to detect potential fabrication faults in complementary metal-oxide semiconductor (CMOS) circuits. Static current testing is based on an assumption that a fault-free CMOS circuit draws very little supply current in a steady state. This current is know as “leakage” current. Certain manufacturing faults on an integrated circuit cause unwanted shorts within the devices fabricated on the integrated circuit. Under certain test A conditions, these shorts can cause an increase in the current drawn by the integrated circuit. A faulty integrated circuit often draws current that is several orders of magnitude greater than that drawn by a non-faulty integrated circuit. Therefore, the leakage current drawn by an integrated circuit under certain test conditions can be used to indicated the presence of a manufacturing defect in the circuit.
Static current testing is performed by applying test vectors to the integrated circuit and making multiple current measurements during a quiescent state of the circuit. A test vector is typically applied to the circuit by serially shifting the test vector into the circuit through a chain of “scannable” elements and then clocking the circuit. The test vectors that are used for static current testing must contain vectors that will put the circuit into a low drain current (I
DD
) state. Static current testing is often referred to as I
DDQ
testing.
Once the circuit is in the desired state, the circuit is “strobed” near the end of a period's clock cycle. That is, a snap shot of the circuit is taken, and the status of selected pins and nets is recorded along with the stability of the circuit. The strobe point for each I
DDQ
test vector is usually the last time unit in the clock cycle. If the state of the circuit at a particular strobe point is such that a defect-free chip in that state would not draw supply current, then the test vector and the resulting test patterns obtained at that strobe point can be successfully used for I
DDQ
testing.
When selecting which test vectors should be used for static current testing of an integrated circuit, the response of the circuit to the potential test vectors is simulated on a functional model of the integrated circuit. Each test vector is scanned into the functional model, the model is then “clocked” and the resulting states on selected nodes within the model are recorded at multiple instants in time. The recorded states are output in the form of a value change dump (VCD) file. The states in the VCD file are then analyzed to determine whether the particular vector is a candidate for I
DDQ
testing. An I
DDQ
analyzer checks the states of the circuit against a set of rules to determine whether the circuit would draw current in that state. If not, the vector producing that state is a potential test vector for the I
DDQ
test.
A difficulty arises in selecting potential test vectors for integrated circuits having embedded memory devices. In some integrated circuit designs, it may be desirable for a memory bus have more address bits than are required to address the maximum number of rows actually present in the memory. For example, an integrated circuit design having three address bits can address eight memory locations. However, the actual number of addressable rows in the memory could be less than eight, such as six. In this case, if the test vector sets the states of the address bits such that the address bits address memory locations that do not physically exist in the memory, leakage current can flow through the sense amplifiers. This makes it more difficult to select valid test vectors for static current testing.
In order to avoid addressing memory locations that do not physically exist, the current approach toward solving this problem is to restrict the integrated circuit design to have memories that conform to the maximum addressable size of the address buses on the integrated circuit. This approach leaves the semiconductor designer with very few choices in terms of memory size. As a result, the semiconductor designer may have to use a memory having more rows than is required for the particular design in order for the memory to conform to the maximum addressable size of the address bus. Increasing the memory size results in consumption of costly silicon space and an increase in power consumption.
SUMMARY OF THE INVENTION
One embodiment of the present invention is directed to a method for analyzing a test vector for use in measuring static current consumed by an integrated circuit having an embedded memory device. According to the method, a potential test vector is applied to a functional model of the integrated circuit. The logic states of various nodes in the integrated circuit are detected in response to the potential test vector. At least some of the nodes correspond to the input address bits of the memory device, where the memory device has a valid address range on the input address bits. An output is produced for the potential test vector based on whether these logic states correspond to an address within the valid address range.
Another embodiment of the present invention is directed to a computer readable medium having instructions readable by a programmable computer. The instructions, when executed, cause the computer read a computer file that includes logic states of nodes in a functional model of an integrated circuit, wherein the logic states correspond to a response of the model to a potential static current test vector. The computer compares the logic states of selected ones of the nodes that correspond to input address bits of an embedded memory device on the integrated circuit with a valid address range for that memory device. The computer produces an output for the potential test vector based on whether the logic states represent an address within the valid address range.
Yet another embodiment of the present invention is directed to a computer-aided design tool for analyzing static current test vectors. The tool reads a computer file that includes logic states of nodes in a functional model of an integrated circuit. The logic states correspond to a response of the model to a potential static current test vector. The tool compares the logic states of selected ones of the nodes that correspond to input address bits of an embedded memory device on the integrated circuit with a valid address range for that memory device. The tool produces an output for the potential test vector based on whether the logic states represent an address within the valid address range.
REFERENCES:
patent: 5670890 (1997-09-01), Colwell et al.
patent: 6212655 (2001-04-01), Ghanta et al.
patent: 6449751 (2002-09-01), Hussain et al.
Kaushik De et al., Failure Analysis for Full-Scan Circuits, Proceedings of the International Test Conference, pp. 636-645, Oct. 1995.*
P. Maxwell et al., IDDQ and AC Scan: The War Against UnModelled Defects, Proceedings of the International Test Conferenc pp. 250-258, Oct. 1996.
Ghosh Pradipta
Hussain Hunaid
Thompson A. M.
Westman Champlin & Kelly
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