Method of analyzing semiconductor LSI circuit electrostatic...

Details Method of analyzing semiconductor LSI circuit electrostatic... Method of analyzing semiconductor LSI circuit electrostatic...

2006-09-26

2006-09-26

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07114137

ABSTRACT:
An electrostatic discharge analysis method includes extracting the pads from an input layout of the semiconductor integrated circuit; extracting the nets connected to the extracted pads; extracting the protective elements connected to the extracted nets; forming connection nodes that connect the pads or the protective elements to the nets; extracting for each net, distributed resistances that distribute along the net; connecting the distributed resistances to the connection nodes in place of the nets; forming inter-resistance nodes between the distributed resistances; and calculating an inter-pad voltage when flowing electrostatic discharge current between the pads.

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Li et al., “Full Chip ESD Design Rule Checking,” ISCAS-2001, V-503-V-506, 2001.

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