Method of analyzing DRAM redundancy repair

Details Method of analyzing DRAM redundancy repair Method of analyzing DRAM redundancy repair

2001-09-06

2003-06-03

Allen, Stephone B. (Department: 2878)

Radiant energy

Photocells; circuits and apparatus

With circuit for evaluating a web, strand, strip, or sheet

C382S149000, C356S237500

Reexamination Certificate

active

06573524

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90120813, filed Aug. 24, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of analyzing a dynamic random access memory (DRAM) function. More particularly, the present invention relates to a method of analyzing the correctness of a DRAM redundancy repair.
2. Description of Related Art
Aside from the elements necessary for performing normal dynamic random access memory (DRAM) functions, most arrays also have redundancy elements for repairing defects. This is because some defects are normally produced during the manufacturing process. The so-called ‘redundancy’ refers to a few more rows or columns on a die that have no particular function under the normal situation but can be connected to become an active circuit element should defects occur in the array. To provide a better explanation of the array on a die and the distribution of redundant elements, refer to
FIGS. 1A and 1B
.
FIG. 1A
is a schematic diagram showing an array with redundant elements within a conventional dynamic random access memory die. As shown in
FIG. 1A
, the die includes a normal array
100
and some redundancy elements
102
. After a wafer is designed, the circuit must be tested. If a defective array (the array
120
)
104
appears within the array
100
, a specified program is used to find the defect location before a redundancy repair is carried out.
FIG. 1B
is a schematic diagram showing the array in
FIG. 1A
after a redundancy repair operation. As shown in
FIG. 1B
, a specific program has been used to find the location of the design defect and redundancy rules have been employed to organize data files. Redundancy repair is conducted according to the data within the files. In other words, an array (redundancy)
106
within the redundancy elements
102
will replace the defective array (array
120
)
104
(refer to FIG.
1
A). Ultimately, the defective array (array
120
)
104
inside the normal array
100
is replaced by an effective array (array
12
)
108
.
Hence, redundancy repair is an important means of increasing yield and reducing the number of defects in the manufacturing of DRAM products. However, quite frequently, the DRAM still contains defects after a redundancy repair so that it is difficult to assess whether the circuit design is good or bad. Furthermore, after the repair, it is also quite difficult to ascertain if the defective portions have been properly repaired or the original correct array circuit has been replaced by redundancy elements without solving the defective problem. To ascertain correctness of the redundancy repair, a trial-and-error method is frequently used. In other words, DRAM cells must be repeatedly produced and tested. With repeated production and testing, production time and the number of manufacturing steps are increased.
In addition, to remove the difficulties of deciding whether a particular design is good or bad or whether a particular defect has been correctly repaired after a redundancy repair, a design in test mode is normally executed to inspect the already repaired redundancy data. Otherwise, a large quantity of data and repeated laser inspection need to be conducted. Moreover, the testing mode will increase area occupation of the die leading to a greater production cost.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method of analyzing the correctness of a DRAM redundancy repair. The method is capable of detecting the correctness of a circuit design and indicating whether a defective location is properly repaired or not after a redundancy repair. Ultimately, the manufacturing process is simplified, production time is saved and production cost is reduced.
A second object of this invention is to provide a device for analyzing the correctness of a DRAM redundancy repair. The device is capable of determining if a DRAM redundancy repair is correctly conducted so that production time is saved, manufacturing process is simplified and production cost is saved.
This invention utilizes the characteristics of a DRAM cell to test the correctness of a redundancy repair. The so-called characteristics of a DRAM device refers to the utilization of a convex lens between an automatic pin probe and a light source to focus a light source onto one portion of an area within the die as small as a point. When a particular DRAM cell is illuminated by the spot of light, leakage is intensified and a stored data bit within the DRAM cell having the value ‘1’ is converted to a stored data ‘0’ after some time. This is the so-called refresh time. Utilizing the refresh time test to fail the illuminated array element and to pass the non-illuminated array element, a physical bit map can be projected onto a computer screen.
This invention provides a method of analyzing the correctness of a DRAM redundancy repair. The method utilizes a convergent light beam to illuminate the dies on a wafer and then observes the physical bit map on a monitor after illumination. When the convergent light beam is made to align with the defect location on an array, the monitor will display two semicircular-shaped bright regions. On the other hand, when the convergent light beam is made to align with the redundancy location for conducting a repair, the monitor will display a bright line. According to the bright line and two semicircular-shaped bright regions, correctness of the redundancy repair can be determined.
This invention also provides a device for analyzing the correctness of a DRAM redundancy repair. The device includes an automatic pin probe, a light source and a convex lens. A die to be tested is placed on the automatic pin probe with the light source located directly above. Utilizing the convex lens between the automatic pin probe and the light source to focus the light from the light source onto the die, the beam focuses on the array to be tested.
In brief, this invention provides a method of analyzing the correctness of a DRAM redundancy repair. The method is capable of showing whether the circuit is the correct design and validating the correctness of the coordinates of a defective location so that production time is saved and the manufacturing steps as well as production cost is reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 4806774 (1989-02-01), Lin et al.
patent: 5428442 (1995-06-01), Lin et al.
patent: 5917332 (1999-06-01), Chen et al.

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