Method of analyzing a wafer in a semiconductor device fabricatio

Details Method of analyzing a wafer in a semiconductor device fabricatio Method of analyzing a wafer in a semiconductor device fabricatio

1997-04-24

1999-08-24

Dutton, Brian

Semiconductor device manufacturing: process

Including control responsive to sensed condition

Optical characteristic sensed

438 16, 250309, H01L 2100, H01L 2166, G01R 3126

Patent

active

059435488

ABSTRACT:
A method of analyzing a wafer in a semiconductor device fabrication process, includes the steps of: loading a wafer into a vacuum chamber where the vacuum pressure is maintained at a predetermined level; locating coordinates of a specific portion of the wafer and irradiating a primary ion beam onto the specific portion of the wafer at those coordinates; and detecting an impurity concentration by analyzing the mass of a specific ion from among secondary ions generated by collision of the primary ion beam with the surface of the specific portion of the wafer.

REFERENCES:
patent: 3742227 (1973-06-01), Benninghoven
patent: 4874946 (1989-10-01), Kazmerski
patent: 5086227 (1992-02-01), Toita et al.

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