Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
Reexamination Certificate
2000-07-17
2003-07-15
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Replacement of memory spare location, portion, or segment
Reexamination Certificate
active
06594788
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory testing apparatus for testing various kinds of semiconductor memories including a memory being constructed by, for example, a semiconductor integrated circuit (hereinafter, referred to as IC) and a method of analyzing a relief or repair of failure cell or cells in a memory, which includes the steps of counting the number of failure memory cells of a semiconductor memory tested by this memory testing apparatus and determining whether or not a repair of the tested semiconductor memory is possible. (Hereinafter, a memory being constructed by a semiconductor integrated circuit is referred to as IC memory.) More particularly, the present invention relates to a method of analyzing a repair of failure cell or cells in a memory, which includes the step of determining whether or not a repair of failure called in this technical field “must-repair” in a memory of redundancy structure can be carried out and a memory testing apparatus having a failure relief analyzer using this analyzing method.
2. Description of the Related Art
In recent years, increase of memory capacity and miniaturization of an IC memory have been attempted. Associated with the increased memory capacity and the miniaturization of an IC memory, defect rates of IC memories have been increased. In order to decrease the defect rates, in other words, in order to prevent the yield from being decreased, there have been manufactured, for example, IC memories in each of which failure memory cells can be electrically replaced with spare memory cells (referred to as spare lines, relief lines or a redundancy circuit in this technical field). The IC memories of this type each having spare memory cells are called, in this technical field, memories having redundancy structure, and the determination as to whether or not a relief of failure memory cells of a memory having redundancy structure is possible is performed by a failure relief analyzer. Recently, storage capacity of an IC memory is increasing more and more, and accordingly an increased IC chip area and formation of patterns at high density are required. As a result, there is an increased possibility that a reduction of the yield of IC memories caused by a very minute defect occurs. In order to prevent the yield of IC memories from being reduced, there are manufactured IC memories in each of which, for example, one or more failure memory cells can be electrically replaced by a substitute or alternative memory cell (also called a spare line, relief line or redundancy circuit). As will be described later, the IC memory of this kind is called a memory of redundancy structure in this technical field, and a decision as to whether the redundancy-structured memory can be relieved or not is rendered by a failure relief analyzer.
FIG. 5
is a block diagram showing a schematic configuration of an example of a memory testing apparatus having a conventional failure relief analyzer. This memory testing apparatus TES comprises, roughly speaking, a main controller
111
, a pattern generator
112
, a timing generator
113
, a waveform formatter
114
, a logical comparator
115
, a driver
116
, an analog level comparator (hereinafter referred to as a comparator)
117
, a failure analysis memory
118
, a failure relief analyzer
120
, a logical amplitude reference voltage source
121
, a comparison reference voltage source
122
and a device power source
123
. Further, in the following description, a case of testing an IC memory will be described. However, various semiconductor memories other than IC memories are similarly tested.
The main controller
111
is generally constituted by a computer system in which a test program PM created by a user (programmer) is loaded in advance, and the control of the entire memory testing apparatus is performed in accordance with the test program PM. This main controller
111
is connected, via a tester bus BUS, to the pattern generator
112
, the timing generator
113
, the failure analysis memory
118
, the failure relief analyzer
120
and the like. Although not shown, the logical amplitude reference voltage source
121
, the comparison reference voltage source
122
and the device power source
123
are also connected to the main controller
111
.
An IC memory to be tested (IC memory under test, generally referred to as MUT)
119
is mounted on a socket of a test head (not shown) constructed separately from the memory testing apparatus proper. Usually, a member called a performance board is mounted on the upper portion of the test head, and a predetermined number of IC sockets are mounted on the performance board. Therefore, the IC memory under test
119
is mounted on related one of the IC sockets. In addition, a printed-circuit board called pin card in this technical field is accommodated inside the test head. Usually, a circuit containing the driver
116
and the comparator
117
of the memory testing apparatus TES is formed on this pin card. In general, the test head is mounted on a test section of an IC transporting and processing apparatus called handler in this technical field, and is electrically connected to the memory testing apparatus proper by signal transmission means such as a cable, an optical fiber or the like.
First of all, before starting the test of the IC memory, various kinds of data are set by the main controller
111
. After the various kinds of data have been set, the test of the IC memory is started. When the main controller
111
issues a test starting command to the pattern generator
112
, the pattern generator
112
starts to generate a pattern. The pattern generator
112
supplies a test pattern data to the waveform formatter
114
in accordance with the test program PM. On the other hand, the timing generator
113
generates a timing signal (clock pulses) for controlling operation timings of the waveform formatter
114
, the logical comparator
115
and the like.
The waveform formatter
114
converts the test pattern data supplied from the pattern generator
112
into a test pattern signal having a real waveform. This test pattern signal is applied to the IC memory under test (hereinafter referred to as memory under test)
119
via the driver
116
that amplifies the voltage of the test pattern signal to a waveform having an amplitude value set by the logical amplitude reference voltage source
121
. The test pattern signal is stored in a memory cell of the memory under test
119
having an address specified by an address signal, and the storage content is read out therefrom during a read cycle later on.
A response signal read out from the memory under test
119
is compared with a reference voltage supplied from the comparison reference voltage source
122
in the comparator
117
, and it is determined whether or not the response signal has a predetermined logical level, i.e., whether or not the response signal has a predetermined logical H (logical high) voltage or logical L (logical low) voltage. A response signal determined to have the predetermined logical level is sent to the logical comparator
115
, where the response signal is compared with an expected value pattern signal, and whether or not the memory under test
119
has outputted a normal response signal is determined.
If the response signal is not equal to the expected value pattern signal, a memory cell having an address of the memory under test
119
from which the response signal was read out is determined to be in failure, and a failure signal indicating the failure is generated from the logical comparator
115
. Usually, when a failure signal is generated, a writing of a failure data (generally logical “1” signal) applied to a data input terminal of the failure analysis memory
118
is enabled, and the failure data is stored in an address of the failure analysis memory
118
specified by an address signal being supplied to the failure analysis memory
118
at that time.
The failure analysis memory
118
has an operation speed and a memory capacity equivalent
Abraham Esaw
Advantest Corporation
De'cady Albert
Gallagher & Lathrop
Lathrop, Esq. David N.
LandOfFree
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