Method of aligning layers in an integrated circuit device

Details Method of aligning layers in an integrated circuit device Method of aligning layers in an integrated circuit device

1993-09-30

1996-08-13

Fourson, George

Fishing, trapping, and vermin destroying

437924, H01L 21463

Patent

active

055455930

ABSTRACT:
A method of aligning layers in an integrated circuit device includes associating an alignment target (10, 50) with each layer. Each alignment target (10, 50) has multiple edges created through a boxed frame configuration (16, 18). During semiconductor device fabrication, each alignment target (10, 50) is formed into an alignment structure (200) on the semiconductor wafer. For correspondingly aligned layers, one alignment target of one layer falls within the alignment target of a correspondingly aligned layer within the alignment structure (200). The edges of each alignment target (10, 50) are scanned to determine a center point for each alignment target (10, 50). The layers of the corresponding alignment targets (10, 50) are aligned if the center points calculated from the scanning process performed on the edges of each alignment target coincide along x-axis and y-axis planes.

REFERENCES:
patent: 5260599 (1993-11-01), Ponse et al.
patent: 5316984 (1994-05-01), Leourx
IBM Technical Disclosure Bulletin vol. 31 No. 4 (Sep. 1988). "Digilized Box-in-a-Box Alignment Veriers For Measuring Accuracy of Overlays . . . ".

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