Method of adjusting currents on a semiconductor device having tr

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

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324713, 438 18, 257 48, G06F 1750

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06083272&

ABSTRACT:
A method of adjusting drive currents on a semiconductor device having transistors of various densities is disclosed. Consistent with the invention, off-state currents and drive currents associated with non-dense transistors on a first semiconductor device formed by a fabrication process are determined. Off-state currents associated with dense transistors on the first semiconductor device are also determined. Using the determined off-state and drive currents associated with the non-dense transistors and the off-state currents associated with the dense transistors on the first semiconductor device, drive currents associated with the dense transistors on the first semiconductor device are estimated. One or more parameters of the fabrication process are then adjusted based on the estimated drive currents of the dense transistors on the first semiconductor device in order to calibrate drive currents of dense transistors with drive currents of non-dense transistors on semiconductor devices formed using the fabrication process. The drive currents of the dense and non-dense transistors may, for example, be matched to within about 3 microamps.

REFERENCES:
patent: 5241497 (1993-08-01), Komarek
patent: 5340700 (1994-08-01), Chen et al.
patent: 5401982 (1995-03-01), King et al.
patent: 5637512 (1997-06-01), Miyasaka et al.
patent: 5650979 (1997-07-01), Komarek et al.
patent: 5677867 (1997-10-01), Hazani
patent: 5703382 (1997-12-01), Hack et al.
patent: 5733812 (1998-03-01), Ueda et al.
patent: 5789780 (1998-08-01), Fulford, Jr. et al.
patent: 5789955 (1998-08-01), Scheraga
patent: 5863824 (1999-01-01), Gardner et al.
Venkatesan et al "Device Drive Current Degradation Observed With Retrograde Channel Profiles," IEEE, pp. 17.2.1-17.2.4, Jan. 1995.
Liebmann et al., Understanding Across Chip Line Width Variation: The First Step Toward Optical Proximity Correction, Paper 3051-05, Session 2, (undated) p. 129. No date.
Tritchkov et al., Optical Proximity Effects Correction at 0.25 .mu.m Incorporating Process Variations in Lithography, Paper 3051-27, Session 7, (1994), p. 148-149.
Fujimoto et al., Comparison between Optical Proximity Effect of Positive and Negative Tone Patterns in KrF Lithography, Paper 3051-28, Session 7, (undated), p. 150. No date.
Yasuzato et al., Optical proximity correction of alternating phase shift masks for 0.81 .mu.m KrF lithography, Paper 3051-29, Session 7, (1995), p. 151.
Misaka et al., Optical Proximity Correction in DRAM Cell Using a New Statistical Methodology, Paper 3051-30, Session 7, (undated), pt. 152. No date.

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