Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output addressing
Reexamination Certificate
1999-03-29
2002-04-09
Lee, Thomas (Department: 2782)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output addressing
C710S004000, C710S009000, C710S026000, C710S036000, C710S120000
Reexamination Certificate
active
06370595
ABSTRACT:
FIELD OF THE INVENTION
The present invention concerns a method of addressing units amongst a plurality of units having different addresses by means of an address word, the addresses and the address word being composed of address elements.
The invention also concerns a corresponding system for carrying out the method. The invention may be used in applications related to Multimedia.
BACKGROUND ART
U.S. Pat. No. 5,724,529 describes a computer system comprising means for addressing individual sockets. A PC card controller is associated to a group of sockets, addressed by a processor through an address bus. The controller has a socket pointer that uniquely identifies a socket among a plurality of sockets. A socket is addressed when at least a portion of the pointer information matches a portion of the transmitted address. The system disclosed allows addressing of one unit (socket) at a time. Each address word transmitted from the processor permits the addressing of a single unit. In the case of the addressing of several units with different addresses, the addresses need to be transmitted in series, one at a time. This method of addressing results in long delays when addressing several units.
SUMMARY OF THE INVENTION
It is an object of the invention to ameliorate existing addressing methods by allowing greater flexibility and greater speed in addressing.
To this end, the method such as defined in the preamble comprises the steps of:
transmitting a tag word to the plurality of units, the tag word defining which address elements of the address word are significant and which address elements of the address word are non significant;
comparing the address word and the addresses of the units, a unit being addressed if the significant elements of the address word match the corresponding elements of the unit's address.
This method thus allows addressing of several units at a time by means of a single address word. An advantage of this method is time-efficiency because, in one addressing cycle, several units can be addressed simultaneously without having to address individually and in series each unit. Furthermore the method permits to address at a time an arbitrary group of units among the plurality of units. Thus, advantages of the method are a greater flexibility and a greater speed in addressing.
The invention also relates, for carrying out the method, to a system having:
a plurality of addressable units having different addresses, the addresses being composed of address elements,
wherein the system also comprises
an addressing unit for generating an address word composed of address elements and an associated tag word, the tag word defining which address elements of the address word are significant and which address elements of the address word are non significant;
a bus system for conveying the address word and the associated tag word to the addressable units;
a decoder being associated to each addressable unit for comparing the address word and the address of the unit, the unit being addressed if the significant elements of the address word match the corresponding elements of the unit's address.
REFERENCES:
patent: 4315310 (1982-02-01), Bayliss et al.
patent: 4400774 (1983-08-01), Toy
patent: 4821171 (1989-04-01), Calamari
patent: 5454092 (1995-09-01), Sibigtroth
patent: 6240501 (2001-05-01), Hagersten
Bru Bernard
Duranton Marc
Geslin Loic
Vier Valerie
Lee Thomas
Perveen Rehana
U.S. Philips Corporation
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