Method of achieving narrow V.sub.T distribution after erase in f

Details Method of achieving narrow V.sub.T distribution after erase in f Method of achieving narrow V.sub.T distribution after erase in f

1998-03-09

2000-02-08

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518524, 36518529, G11C 1604

Patent

active

060234261

ABSTRACT:
There is provided a method of correcting overerased memory cells in a flash EEPROM memory cell after erase so as to produce a narrow threshold voltage distribution width. A ground potential is applied to all of the sources and substrates of the cells in the array of memory cells. First positive pulse voltages are simultaneously applied to each word line in a first timed sequence on a word line by word line basis. A second positive pulse voltage is simultaneously applied to each bit line in a second timed sequence in a bit line by bit line basis when the first positive pulse voltages are being applied to a first word line and is then repeated for each subsequent word line until a last word line is applied.

REFERENCES:
patent: 5535158 (1996-07-01), Yamagata
patent: 5574686 (1996-11-01), Watsuji et al.
patent: 5742541 (1998-04-01), Tanigami et al.
patent: 5805499 (1998-09-01), Haddad
patent: 5815438 (1998-09-01), Haddad et al.

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