Method of accelerating test of semiconductor device

Details Method of accelerating test of semiconductor device Method of accelerating test of semiconductor device

2007-01-02

2007-01-02

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C257S669000, C257SE23010

Reexamination Certificate

active

10642222

ABSTRACT:
Semiconductor elements composing a semiconductor device are formed on a semiconductor substrate. Wirings composed of copper or an alloy mainly composed of copper are formed in wiring layers through interlayer insulation films to connect the semiconductor elements to each other. When the wirings are formed, a temperature of the wirings is held in a first temperature zone covering ±40° C. of a temperature at which a stress migration is most accelerated.

REFERENCES:
patent: 5930587 (1999-07-01), Ryan
patent: 6348741 (2002-02-01), Ogino et al.
patent: 6946723 (2005-09-01), Satoh et al.
patent: 2002/0098681 (2002-07-01), Hu et al.
patent: 3-254126 (1991-11-01), None
patent: 10-12687 (1998-01-01), None
K. Yoshida et al., International Electron Device Meeting, pp. 753-756, “Stress-Induced Voiding Phenomena for an Aactural CMOS LSI Interconnects”, Dec. 2002.

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