Method in a processor for performing in-memory tracing using...

Details Method in a processor for performing in-memory tracing using... Method in a processor for performing in-memory tracing using...

2005-02-11

2008-09-02

Bonzo, Bryce P. (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

Reexamination Certificate

active

07421619

ABSTRACT:
A method, apparatus, and computer program product are disclosed for performing in-memory hardware tracing in a processor using an existing system bus. The processor includes multiple processing units that are coupled together utilizing the system bus. The processing units include a memory controller that controls a system memory. Information is transmitted among the processing units utilizing the system bus. The information is formatted according to a standard system bus protocol. Hardware trace data is captured utilizing a hardware trace facility that is coupled directly to the system bus. The system bus is utilized for transmitting the hardware trace data to the memory controller for storage in the system memory. The memory controller is coupled directly to the system bus. The hardware trace data is formatted according to the standard system bus protocol for transmission via the system bus.

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Al-Omari et al., Method, Apparatus, and Computer Program Product in a Processor for Concurrently Sharing a Memory Controller Among a Tracing Process and Non-Tracing Processes Using a Programmable Variable Number of Shared Memory Write Buffers, Feb. 11, 2005.
Al-Omari et al., Method, Apparatus, and Computer Program Product in a Processor for Dynamically During Runtime Allocating Memory for In-Memory Hardware Tracing, Feb. 11, 2005.
Al-Omari et al., Method, Apparatus, and Computer Program Product for Synchronizing Triggering of Multiple Hardware Trace Facilities Using an Existing System Bus, Feb. 11, 2005.
Al-Omari et al., Method, Apparatus, and Computer Program Product in a Processor for Balancing Hardware Trace Collection Among Different Hardware Trace Facilities, Feb. 11, 2005.

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