Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-04-01
1999-06-01
An, Men-Ai T.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
395829, 711 4, 711112, 711203, G06F 1200
Patent
active
059095920
ABSTRACT:
A method of recognizineg peripheral devices coupled to an interface such as an Integrated Device Electronics interface provides a logically sequential addressing scheme for peripheral devices that may not have physically contiguous or sequential addresses. The method enables operating systems that otherwise only support sequentially ordered drives to support access to devices coupled to the interface in any order. The method includes the step of copying a basic input/output (BIOS) device configuration table and a (BIOS) device parameter table into memory. The existence of any device coupled to the interface is tested using every physical device identifier supported by the size of the device configuration table. For each detected device 1) the configuration table is modified to indicate that the detected device is coupled to the interface, wherein the detected device is assigned a logical identifier sequential to that of any previously detected device; and 2) the device parameter table is modified to indicate parameters associated with the detected device. Thereafter, a specified device identifier is translated to a specified physical device identifier in response to an operating system request to access a selected device identified by the specified device identifier. The specified physical device identifier is then used to access a specified physical device in accordance with the configuration and device parameter tables.
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An Men-Ai T.
Intel Corporation
Lefkowitz Sumati
LandOfFree
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