Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1998-10-30
2001-07-24
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S201000, C711S220000
Reexamination Certificate
active
06266747
ABSTRACT:
TECHNICAL FIELD
This disclosure relates to the field of computer systems and more particularly to a method of writing data into data storage units in such computer systems.
BACKGROUND
Under a typical computer system architecture, during read and write cycles, a data storage controller (DSC) controls access to data storage units (DSUs) that comprise system memory with addressable memory locations, which are generally within a continuous range of predefined logical addresses. For accessing the system memory, the DSC processes read and write requests generated by an instruction processing unit (IPU) executing a program that requests data to be read from or written into a particular memory location. Upon receipt of the requests, the DSC initiates corresponding read or write cycles over a memory bus, for accessing the addressed memory locations. The rate by which data is transferred, i.e., the data throughput, during each memory cycle is dependent on the bus speed as well as the width of the system's data bus and the length of a memory location, which is defined in terms of data bits, for example, 8-bit, 16-bit, or 32-bit, etc.
Each memory cycle, read or write, expends a certain number of clock cycles. Because the performance of a computer system is highly dependent on the data throughput, it is necessary to maximize the data transfer rate over the memory bus, ideally, making it reach the full system clock speed. Various techniques have been devised to increase the data throughput by minimizing the time required to access the system memory. For example, under an scheme known as interleaved memory access, each DSU is addressable over a corresponding internal bus that has an assigned range of physical addresses. In this way, a memory accesses over one internal bus can start ahead of completion of a prior access over another internal bus, provided that the memory bus bandwidth supports the execution of parallel memory accesses over the internal busses. Usually, under the interleaved memory access arrangement, a separate memory management unit (MMU) maps the logical memory addresses into the physical addresses.
Although the interleaved write scheme improves data throughput for writing into separate physical addresses, sometimes the execution of a program requires writing data to the same address, with each write request sometimes modifying different portions of the memory address. For example, two back-to-back writes to a two-word (32 bits) address location may modify a first nibble (4 bits) in bit positions 0-3, and a third nibble in bit positions 16-19. Under a conventional arrangement two write cycles must be initiated to service the write requests to the same address. It is, however, desired to reduce the number of write cycles to different portions of the same memory address, in order to increase data throughput for accessing the system memory.
SUMMARY OF THE INVENTION
Briefly, the present invention is embodied in a method for writing data variables into a system memory that has addressable memory locations, with each memory location having corresponding memory positions. After the data variables to be written are received, the method of the invention generates mask bits that correspond to the specified memory positions into which the received data variables are to be written. The received data variables and their corresponding mask bits are merged, unless a condition for not merging the data variables is satisfied. If so, then the merged data variables are written into the system memory. The condition for not merging the data variables is satisfied either when a memory address for a current data variable to be written is not the same as that of a previous data variable, or when two successive data variables are to be written into two separate portions of the same memory location for example, an upper 16-portion and a lower 16-bit portion, or when a read request for a data variable from a memory address becomes dependent on a pending write request that writes a data variables into the same memory address.
According to some of the more detailed features of the invention, the data variables are merged based on a predefined bit length format and a data start position within the memory location. In the exemplary embodiment of the invention, the predefined bit length format may specify a data variable as a 1-bit, 2-bit, 4-bit, 16-bit, 32-bit, 64-bit, or 128-bit data variable. Based on the predefined bit length format, a data variable may be written into different memory locations, without being merged with another data variable. For example, a 32-bit data variable is written into the system memory without being merged with another data variable. The 64-bit and 128-bit data variables are fragmented into a corresponding plurality of 32-bit data variables, with each 32-bit variable being written without merging. Under one aspect, the method of the invention generates a mask position field (MPO) defining whether a data variable should be written into a first portion or a second portion of a memory location, for example, the upper or lower 16-bit portions. In this way, by decoding an instruction based on the MPO, a determination is made as to whether a data variable should be written into a lower word of an addressed memory location, an upper word of an addressed memory location, or the entire length of an addressed memory location.
REFERENCES:
patent: 4520439 (1985-05-01), Liepa
patent: 4750154 (1988-06-01), Lefsky et al.
patent: 4868553 (1989-09-01), Kawamata
patent: 5488709 (1996-01-01), Chan
patent: 5590348 (1996-12-01), Phillips et al.
patent: 5592684 (1997-01-01), Gaskins et al.
patent: 5745732 (1998-04-01), Cherukuri et al.
patent: 0651331A (1995-05-01), None
“Gathering Store Instructions in a Superscaler Processor” IBM Technical Disclosure Bulletin, vol. 39, No. 9, Sep. 1996, pp. 103-105.
Dahl Orvar Per
Zervens Matiss Jonas
Burns Doane Swecker & Mathis L.L.P.
Moazzami Nasser
Telefonaktiebolaget LM Ericsson (publ)
Yoo Do Hyun
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