Method for writing data into a semiconductor memory device...

Details Method for writing data into a semiconductor memory device... Method for writing data into a semiconductor memory device...

2002-04-01

2003-12-30

Tran, M. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S202000

Reexamination Certificate

active

06671201

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to a method for writing data into a semiconductor memory device and more particularly to a method for writing data into a semiconductor memory device such as a SRAM (static random access memory) that may include a memory cell operating at a relatively low voltage.
BACKGROUND OF THE INVENTION
It is a continuing goal to improve the bit density and decrease power consumption in a semiconductor memory device. One method of increasing the bit density is to decrease the size of the memory cell. In a SRAM (static random access memory), the size of the memory cell may be decreased by including memory cell transistors having a smaller size.
In order to decrease power consumption and improve breakdown reliability of memory cells having small sizes, memory cells receive a relatively low power supply voltage. For example, in a SRAM having memory cells configured with MOS (metal oxide semiconductor) transistors, the memory cells may operate using a power supply voltage as low as 1.2 V.
A configuration of a conventional SRAM will now be discussed.
FIG. 4
is a circuit schematic diagram illustrating a portion of a conventional SRAM given the general reference character
10
.
Referring to
FIG. 4
, conventional SRAM
10
has a memory cell
20
. Memory cell
20
stores a data logic value. Although not shown, conventional SRAM includes an array (matrix) of memory cells
20
arranged in rows and columns. Conventional SRAM
10
includes a write circuit
30
for writing data into memory cell
20
. A word line WL is connected to a row of memory cells
20
. Bit lines (BL
0
and BL
1
) are connected to a column of memory cells
20
and write circuit
30
. Although not shown, a plurality of bit lines and a plurality of word lines are included that respectively connect columns and rows of memory cells.
Memory cell
20
includes inverters (
21
and
22
) and transfer gates (Qn
31
and Qn
32
). Inverter
21
has an input connected to node C
2
and an output connected to node C
1
. Inverter
22
has an input connected to node C
1
and an output connected to node C
2
. In this way, inverters (
21
and
22
) form a bi-stable flip-flop that stores a data value and inverted data value at respective nodes (C
1
and C
2
).
Inverters (
21
and
22
) are CMOS (complementary MOS) type inverters. Inverter
21
includes a NMOS transistor Qn
1
and a PMOS transistor Qp
1
. NMOS transistor Qn
1
has a source connected to ground, a drain connected to node C
1
and a gate connected to node C
2
. PMOS transistor Qp
1
has a source connected to an array power supply, a drain connected to node C
1
and a gate connected to node C
2
. Inverter
22
includes a NMOS transistor Qn
2
and a PMOS transistor Qp
2
. NMOS transistor Qn
2
has a source connected to ground, a drain connected to node C
2
and a gate connected to node C
1
. PMOS transistor Qp
2
has a source connected to an array power supply, a drain connected to node C
2
and a gate connected to node C
1
.
Transfer gates (Qn
31
and Qn
32
) may each be a NMOS transistor. Transfer gate Qn
31
has a first source/drain terminal connected to bit line BL
1
, a second source/drain terminal connected to node C
1
, and a control gate connected to word line WL. Transfer gate Qn
32
has a first source/drain terminal connected to bit line BL
0
, a second source/drain terminal connected to node C
2
, and a control gate connected to word line WL.
When data is written into memory cell
20
, write circuit
30
applies a high voltage level to one bit line (BL
0
and BL
1
) while applying a low level (ground or 0V) to the other bit line (BL
0
or BL
1
) while a word line driver (not shown) applies a high potential to word line WL (thus selecting memory cell
20
).
As an example, assuming data is stored in memory cell
20
so that node C
1
has a high level and node C
2
has a low level. A low level on node C
2
is inverted by inverter
21
to keep node C
1
high and the high level on node C
1
is inverted by inverter
22
to keep node C
2
low. In this way, the data is latched and stored in memory cell
20
.
Now, assuming opposite data is written into memory cell
20
. Word line WL is driven high, thus turning on transfer gates (Qn
31
and Qn
32
). Write circuit
30
then applies a low level to bit line BL
1
and a high level to bit line BL
0
. Because transfer gates (Qn
31
and Qn
32
) are NMOS transistors, they provide an efficient pull down, but an inefficient pull up capability. Thus, the high level applied to bit line BL
0
hardly contributes to the writing. The low level applied to bit line BL
1
pulls node C
1
towards the ground potential through transfer gate Qn
31
. Once node C
1
is driven below a threshold voltage of inverter
22
, inverter
22
pulls node C
2
towards the high level.
When data is read from memory cell
20
, word line WL is driven high and transfer gates (Qn
31
and Qn
32
) are turned on. With transfer gates (Qn
31
and Qn
32
) turned on, memory cell
20
will drive bit lines (BL
0
and BL
1
) in accordance with a stored data value. For example, assuming node C
1
is at a low level and node C
2
is at a high level, the low level at node C
1
pulls down bit line BL
1
while bit line BL
2
may remain at a precharged high level. The signals on bit lines (BL
0
and BL
1
) are then amplified by a sense amplifier (not shown). In this way, data stored in memory cell
20
is read out and provided externally from conventional SRAM
10
.
In a SRAM memory cell, a threshold voltage V
TH
of the NMOS transistors are set relatively high in order to prevent data from being disturbed due to noise. However, if the threshold voltage V
TH
is set too high, the time required for data to be written into the memory cell can become excessive. As an example, when the power supply voltage (VDD) of the memory cell array is 1.2 V, then the threshold voltage V
TH
is set to about 0.5 V.
When a conventional SRAM
10
as illustrated in
FIG. 4
operates at a low power voltage (such as VDD=1.2V), any variations of applied signals from the power supply level or ground level can have considerable effects on the operation.
For example, assume data is to be written to memory cell
20
such that bit line BL
0
is at a high level and bit line BL
1
is at a low level. Word line WL is driven to a high level. However, due to a resistance of the bit line, the low level of bit line BL
1
may be above the ground level. In this case, the current drive (pull down) of transfer gate Qn
31
is reduced. Assuming memory cell
20
originally stored opposite data to what is being written, the potential at node C
1
is determined by a ratio of the current drive (pull-up strength) of PMOS transistor Qp
1
versus the current drive (pull-down strength) of transfer gate Qn
31
. With the current drive of transfer gate Qn
31
reduced, the time required to switch node C
1
from a high level to a low level can become excessive. Also, because inverter
22
drives node C
2
based on the logic level of node C
1
, the time required to switch node C
1
from a low level to a high level can also become excessive. Thus, the overall write cycle time of conventional SRAM
10
may be adversely affected.
FIG. 5
is a timing diagram illustrating writing data into memory cell
20
in conventional SRAM
10
under various conditions.
FIG. 5
includes a clock signal CLK (a timing clock necessary for the proper operation of the SRAM), word line WL signal, and bit line BL
1
signal. Lines (C
1
and C
2
) indicate signals at nodes (C
1
and C
2
), respectively, when bit line BL
1
is driven completely to the ground potential (0.0 V) during a write operation. Lines (C
1
′ and C
2
′) indicate signals at nodes (C
1
and C
2
), respectively, when bit line BL
1
is driven only to 0.2 V over the ground potential. In this case, the time (cell inversion time) between a mid-point (0.5 VDD) of a high transition of the word line WL and a 90 percent point (0.9 VDD) of a transition of node C
2
(line C
2
′) to a high level is much longer than the case (line C
2
) when

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