Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
2002-01-18
2004-02-03
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S225700, C365S207000
Reexamination Certificate
active
06687168
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method and apparatus for writing data bits to a memory array.
BACKGROUND ART
In nearly every electronic and computer device and/or system, there are memory components and elements which are used in conjunction with the storing of data/information. This data/information may be, but is not limited to, operating system instructions, currently used data, or data that is to be archived and retained within a memory component or data storage device, and the like.
To provide for the storage of data that is to be archived, non-volatile data storage devices were developed to provide data storage. Permanently stored data, commonly termed archived data, only needs to be written once to memory, and can then be read many times. One example of memory that can provide data storage is commonly referred to as WORM (write once read many) memory. Another example of memory that can provide data storage is rewriteable memory.
Unfortunately, previous data storage devices such as hard disks, floppies, and CD-RWs, etc., are now commonly larger in size than many of the handheld computer systems and digital devices so prevalent today.
Accordingly, to provide data storage for the more diminutive computers and digital devices, newer and smaller sized data storage devices have been developed. Further, these newer data storage devices need to have storage capacities sufficient for the storing for digital images and digital audio.
One such data storage device recently developed is flash memory. One form of flash memory is that which is compatible with PCMCIA standards. Another form of flash memory is that which is compatible with a Compact Flash card standards. In yet another form, the flash memory is very similar in function to a miniature floppy disk, but with a much greater storage capacity. A floppy disk has a capacity of 1.44 MB (megabytes) whereas this form of flash memory can have a capacity that ranges from 8 MB up to 128 MB, or more, of storage space, which is more than adequate for most images, audio files, and/or the archiving of data. This type of flash memory is commonly referred to as an SD (secure digital) card, an MMC (multi-media card), or a memory stick. This type of flash memory is becoming more and more prevalent in today's electronic devices, e.g., digital cameras, printers, MP3 players, PDA's, and the like.
The memory section of the flash memory is called the array, or a crosspoint array, or a crosspoint matrix. A crosspoint array or matrix is an arrangement of signal circuits in which input buses are represented by vertical parallel lines and output buses are represented as overlapping horizontal parallel lines. Crosspoint switches at each of the intersecting points connect the inputs with the outputs. Within the crosspoint array, there are a multitude of memory cells. The number of memory cells is dependent upon the size of the array, and can range from as few as a couple of hundred to millions or billions of memory cells. For an electronic device/system and/or a computer system to utilize the memory cells within a memory component, there exists a necessity to be able to read and write data bits to and from the memory cell.
It is commonly known that the writing of data bits can be accomplished by a switching of the power supply voltage to a substantially higher level. While this increase in power supply voltage does, in fact, enable the writing of data bits, it is not without certain drawbacks. Because of the need to increase the power supply voltage to provide data bit writing functionality, numerous ways to provide the increased power supply voltage have been attempted.
In one example, an additional power supply, separate from the first power supply, is implemented. The additional power supply uses a portion of the remaining critical real estate within the electronic device and additional power is needed to operate the additional power supply. While the additional power supply enables data bit writing, by having to account for and to accommodate the power supply within the electronic device, the size of electronic device into which it would be placed may have to be increased, which can add to the overall cost of the device. Further, because the additional power supply requires additional power for it to operate, it may have a detrimental effect upon the capacity of the first power supply. This is especially critical in those electronic devices where the power is derived from batteries or rechargeable power sources. By requiring additional power from the limited retained energy source to power both power supplies, battery replacement or recharging can become more frequent.
In another attempt, a means to significantly change the output of a single power supply is implemented. This is accomplished through the addition of a variety of components and related circuitry, such as amplifiers, transistors, diodes, and the like. While enabling data bit writing, it would, by virtue of the inherent propagation delays within each of the additional components, be a slow-responding process. Additionally, the increase in required real estate to accommodate the added components and circuitry could negatively impact the size of the electronic device. Further, in most cases, the additional components and circuitry would require additional power to be provided to ensure their proper operation. As such, in electronic devices and computer systems that operate on batteries or a rechargeable power source, this could cause an increase in the frequency with which the batteries are replaced or the power source is recharged.
Further, during the writing process, it is common to apply power to the entire crosspoint array. While writing, power is being unnecessarily wasted as only some of the memory cells within the array are written to at any one time. As such, when writing to an array in this manner, where the electronic device or computer system is powered by a battery or a rechargeable power source, this power waste may cause an increase in the frequency with which battery or the rechargeable power source is replaced or recharged, respectively.
Thus, it would be beneficial to be able to write a data bit to a cell in a memory array where additional power sources are not required. It would also be beneficial to use existing components and circuitry when writing to a memory array. It would be further beneficial to write to a cell in a memory array where power is applied to those portions of the array to which the data bit is being written.
DISCLOSURE OF THE INVENTION
Therefore, embodiments of the present invention are drawn to providing a method and apparatus for writing data bits to a memory array.
In one method embodiment, a first input is received. This causes an application of high power, via a sense line, to an addressed bit in the memory array and causes a write operation to be applied to the addressed bit. A second input is received. This causes an application of low power, via said sense line, to the addressed bit and causes a read operation on the addressed bit. The sense line is used to read and write the addressed bit.
In one embodiment, the present invention provides a circuit for writing data bits to a memory array comprising a power source for providing voltage potential and current to said circuit and coupled thereto, an input line for receiving inputted data bit values is coupled to a logic inverter, a plurality of first transistors having first leads coupled to the input line, a plurality of second transistors having first leads coupled to an output of the logic inverter, a plurality of sense lines coupled to other leads of the first and the second plurality of transistors and coupled to the memory array, a plurality of sense amplifiers coupled to other leads of the first and the second plurality of transistors, and a plurality of address lines coupled to the memory array and coupled to the sense lines enabling writing of said data bit to an addressed bit of said memory array.
REFERENCES:
patent: 5173873 (1992-12-01), Wu et al.
paten
Hewlett--Packard Development Company, L.P.
Lebentritt Michael S.
Nguyen Nam
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