Method for wafer level testing of semiconductor using...

Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state

Reexamination Certificate

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C438S467000, C438S601000

Reexamination Certificate

active

06911357

ABSTRACT:
The present invention provides a method and apparatus which facilitates wafer level burn-in testing of semiconductor dies. Sacrificial busses on the wafer supply voltage to respective on die Vcc and Vss sacrificial voltage pads during burn-in testing. The Vcc sacrificial pad on each die is connected to a secondary Vcc pad through an on-die sacrificial metal bus. An on-die fuse is interposed between the secondary Vcc pad and a normal Vcc die bonding pad. The fuse will blow when a die draws excessive current isolating a defective die from other dies on the wafer which are connected to the sacrificial busses. The Vss sacrificial pad is connected to a normal Vss die bonding pad through a sacrificial metal bus. After burn-in testing, the structures are removed. During this removal, the on-die sacrificial metal busses protect the secondary Vcc pad and Vss bonding pad. The secondary Vcc pad, Vcc bonding pad and Vss bonding pad can then be exposed for additional die testing.

REFERENCES:
patent: 5391892 (1995-02-01), Devereaux et al.
patent: 5859792 (1999-01-01), Rondeau, II et al.
patent: 5923047 (1999-07-01), Chia et al.
patent: 6091079 (2000-07-01), Green et al.
patent: 07092221 (1995-04-01), None

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