Method for voltage drop analysis in integreted circuits

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

10838809

ABSTRACT:
A method for performing a voltage drop analysis in a logic circuit that takes into consideration voltage drop—current drain dependency. The voltage drop analysis helps in accurately estimating power requirements of the logic circuit, designing optimal power grids and performing accurate static timing analysis for the logic circuit. The logic circuit has a plurality of gates. The method generates polynomial models for the power consumption, delay and transition time of each gate in the logic circuit. Thereafter, the polynomial models are solved to determine the supply voltage available at each gate of the logic circuit. The supply voltage, thus determined, is used to perform voltage drop analysis.

REFERENCES:
patent: 5787011 (1998-07-01), Ko
patent: 6678869 (2004-01-01), Ohkubo
patent: 6937971 (2005-08-01), Smith et al.
patent: 2004/0249588 (2004-12-01), Shimazaki et al.
Feng Wang and Shir-Shen Chang, Scalable Polynomial Delay Model for Logic and Physical Synthesis, International Conference on Chip Design Automation (ICDA) Conference 2000, Session 12 (available at http://www.ifip.or.at/con2000/icda-12-6.pdf.

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