Method for VLSI system debug and timing analysis

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

07114136

ABSTRACT:
A method for characterizing circuit activity in an IC. Generally, the method comprises the steps of activating an IC, resolving the switching activity in space and time, and generating a representation of the switching behavior which differentiates the time that circuits or transistors switch. One embodiment of the invention, utilizes a method such as, but not limited to, time resolved photon emission to observe transistor level switching activity in an integrated circuit (IC).

REFERENCES:
patent: 5682104 (1997-10-01), Shido
patent: 5825191 (1998-10-01), Niijima et al.
patent: 5940545 (1999-08-01), Kash et al.
patent: 6608494 (2003-08-01), Bruce et al.
patent: 6650768 (2003-11-01), Evans et al.
Howard, R.E. et al., “Single Electron Switching Events in Nanometer-Scale Si MOSFET's”, IEEE Transactions on Electron Devices, vol. ED-32, No. 9, Sep. 1985, pp. 1669-1674.

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