Method for verifying that a processor is executing...

Details Method for verifying that a processor is executing... Method for verifying that a processor is executing...

1998-10-30

2001-08-21

Ray, Gopal C. (Department: 2181)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C712S043000

Reexamination Certificate

active

06279126

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a computer program that verifies the proper operation of a processor. More specifically, the present invention relates to a computer program that verifies that instructions are executed in a proper endian mode when the endian mode is changed dynamically.
DESCRIPTION OF THE RELATED ART
Versions 1.1 and 2.0 of the Hewlett-Packard Precision Architecture Reduced Instruction Set Computer (PA-RISC) architecture provide for a an E-bit in the Processor Status Word (PSW) that enables memory references to data and instructions to have either big or little endian byte ordering. The PA-RISC 1.1 and 2.0 Architecture and Instruction Set Reference Manuals are hereby incorporated by reference. When the E-bit is 0, all larger-than-byte loads and stores are big endian, with lower-addressed bytes in memory corresponding to the higher-order bytes of the register into which the memory operand is loaded. When the E-bit is 1, all larger-than-byte loads and stores are little endian, with the lower-addressed bytes in memory corresponding to the lower-order bytes of the register into which the memory operand is loaded. Loads and stores that are only a single byte are not affected by the E-bit. The E-bit also affects instruction fetching.
Historically, computer systems based on the PA-RISC architecture use big endian. One of the primary purposes of the E-bit is to allow data and programs to be easily migrated from a system that uses little endian to a PA-RISC platform. For example, if a customer has a database application written for an Intel® platform, which uses little endian, the customer can easily re-compile the application and data to execute on a PA-RISC platform without having to re-code the portions of the application that manipulate the data in little endian format.
FIG. 1
illustrates how data is loaded from memory into a register in big endian format. Memory map
10
shows an example of data stored in memory. Bytes a, b, c, d, e, f, g, and h are stored at memory locations
0
,
1
,
2
,
3
,
4
,
5
,
6
, and
7
, respectively. Instruction
12
is a “load byte” instruction that loads the byte at memory location
1
into register
14
. Accordingly, byte b is stored in bit positions
24
-
31
of register
14
. Instruction
16
is a “load half-word” instruction that loads two bytes starting at location
2
into register
18
. Accordingly, byte c is loaded into bit positions
16
-
23
of register
18
, and byte d is loaded into bit positions
24
-
31
of register
18
. Instruction
20
is a “load word” instruction that loads four bytes starting at location
4
into register
22
. Accordingly, byte e is loaded into bit position
0
-
7
of register
22
, byte fis loaded into bitpositions
8
-
15
of register
22
, byte g is loaded into bit position
16
-
23
of register
22
, and by is loaded into bit positions
24
-
31
of register
22
. Finally, instruction
24
is a “floating point load double-word” instructions that loads 8 bytes starting at location
0
into register
26
. Accordingly, byte a is loaded into bit positions
0
-
7
of register
26
, byte b is loaded into bit positions
8
-
15
of register
26
, byte c is loaded into bit positions
16
-
23
of register
26
, byte d is loaded into bit positions
24
-
31
of register
26
, byte e is loaded into bit positions
32
-
39
of register
26
, byte f is loaded into bit positions
40
-
47
of register
26
, byte g is loaded into bit positions
48
-
55
of register
26
, and byte h is loaded into bit positions
56
-
63
of register
26
.
In contrast,
FIG. 2
illustrates how data is loaded from memory into a register in little endian format. Memory map
10
is the same memory map
10
shown in FIG.
1
. Instruction
28
is a “load byte” instruction that loads the byte at memory location
1
into register
30
. Accordingly, byte b is stored in bit positions
24
-
31
of register
30
, which is the same as big endian format. Instruction
32
is a “load half-word” instruction that loads two bytes starting at location
2
into register
34
. Accordingly, in little endian byte d is loaded into bit positions
16
-
23
of register
34
, and byte c is loaded into bit positions
24
-
31
of register
34
. Instruction
36
is a “load word” instruction that loads four bytes starting at location
4
into register
38
. Accordingly, in little endian format byte h is loaded into bit position
0
-
7
of register
38
, byte g is loaded into bit positions
8
-
15
of register
38
, byte f is loaded into bit position
16
-
23
of register
38
, and byte e is loaded into bit positions
24
-
31
of register
38
. Finally, instruction
40
is a “floating point load double-word” instructions that loads 8 bytes starting at location
0
into register
42
. Accordingly, in little endian format byte h is loaded into bit positions
0
-
7
of register
42
, byte g is loaded into bit positions
8
-
15
of register
42
, byte f is loaded into bit positions
16
-
23
of register
42
, byte e is loaded into bit positions
24
-
31
of register
42
, byte d is loaded into bit positions
32
-
39
of register
42
, byte c is loaded into bit positions
40
-
47
of register
42
, byte b is loaded into bit positions
48
-
55
of register
42
, and byte a is loaded into bit positions
56
-
63
of register
42
.
As mentioned above, the E-bit also affects instruction fetching. PA-RISC instructions are four bytes (or alternatively, 32-bits) wide, so the state of the E-bit affects instruction fetching in a manner similar to the “load word” instructions shown in
FIGS. 1 and 2
. When the E-bit is 0, instruction fetch is big endian and the lower addressed bytes in memory correspond to the higher-order bytes in the instruction. When the E-bit is 1, instruction fetch is little endian and the lower-addressed bytes in memory correspond to the lower-order bytes in the instruction.
Architecturally, the instruction byte swapping can occur either when a cache line is moved into the instruction cache or as instructions are fetched from the instruction cache into the pipeline. Because PA-RISC processors are allowed to swap instructions as they are moved into the instruction cache, software is required to keep track of which pages might have been brought into the instruction cache in big endian form and in little endian form. Before executing code, all instruction cache lines of any page that might have been moved into the instruction cache in the wrong form must be flushed from the instruction cache.
One unique aspect of PA-RISC instruction encodings is that an instruction that is valid in big endian mode, may be a different valid instruction in little endian mode. For example, the following PA-RISC instructions having encodings that are valid in both modes:
Big Endian Mode
Little Endian Mode
b,n .+0xdc
addb, tr rl, r16, .+0x7c
addi 4, r0 ,r0
comclr r0, r0, r21
add r31, r9, r9
addco, <> r6, r0, r9
rsm 0x1f, r0
stb r14, 3968 (r0)
1dil 1%0xdead1000, r1
zdep, = r11, 30, 32, r15
1di 26,0
1di 26,0
Note that the encoding of the last instruction “ldi 26,0” is the same in both little and big endian modes. In other words, this instruction is “palindromic”. The fact that some instructions are valid in both modes makes it very hard to verify that the processor is functioning properly when switching dynamically between endian modes
SUMMARY OF THE INVENTION
The present invention is a method for verifying that a processor is executing instructions in a proper endian mode when the endian mode is changed dynamically. In accordance with the present invention, a test suite written and compiled in big endian mode is loaded into memory. The test suite is converted to little endian mode and stored back to memory. Next, the processor status is changed from big endian mode to little endian mode, and the test suite is executed. Finally, the results of the test suite are examined to ensure that the processor properly executed the instructions in little endian mode.
The present invention serves as an important test in a large test suite desig

Affiliated with

Also associated with

Rating

Method for verifying that a processor is executing... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for verifying that a processor is executing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for verifying that a processor is executing... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2488742