Method for verifying properties of a circuit model

Details Method for verifying properties of a circuit model Method for verifying properties of a circuit model

2006-03-28

2006-03-28

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07020856

ABSTRACT:
Methodology for verifying properties of a circuit model in context of given environmental constraints is disclosed. Verification of a specified property is performed by analyzing only a portion of the circuit model. The present methodology is also directed towards reducing the computation time for verifying the specified property. Further, the present methodology allows the connection of an additional circuit model to the circuit model in a non-intrusive manner. The connection is made without making any modifications to the description of the circuit model. This permits the straightforward specification of related environmental constraints and properties, which makes it possible to verify correct behavior of complex interfaces.

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Kushan, R., “Model Checking And Abstraction*,” SARA 2002, LNAI 2371, 2002, pp. 1-17.

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