Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2005-05-24
2005-05-24
Cao, Chun (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S502000, C710S022000, C710S034000, C714S048000
Reexamination Certificate
active
06898723
ABSTRACT:
A method for verifying clock signal frequency of a sound interface of a computer system is disclosed. The processes include steps of initializing and setting a DMA controller and the sound interface, starting DMA data transfer, resetting a time out counter. During the DMA data transfer, a step of incrementing the time out counter is performed until the selected DMA channel of the DMA controller reaches a terminal count condition. After each increment, it is checked if DMA data transfer is time out. When the DMA channel of the DMA controller reaches the terminal count condition, the current count of the time out counter is compared with a maximum tolerable count and a minimum tolerable count. If the count of the time out counter is between the maximum and minimum tolerable counts, a message indicating the clock signal frequency of the sound interface is correct is issued, otherwise a message indicating the clock signal frequency is incorrect is issued.
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Cao Chun
Mitac International Corp.
Rosenberg , Klein & Lee
LandOfFree
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