Method for verification of gate level netlists using colored...

Details Method for verification of gate level netlists using colored... Method for verification of gate level netlists using colored...

2007-05-01

2007-05-01

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

11009350

ABSTRACT:
The present invention relates to the field of computer hardware locic circuits, and in particular to a method for verifying the proper operation of a digital logic circuit, and in particular to symbolic simulation of a gate-level netlist corresponding to said hardware logic circuit. In order to add a useful alternative in the field of functional, exhaustive simulation and of symbolic simulation, it is proposed to perform the steps of:a) analyzing symbolic expressions visible at predetermined locations within said logic;b) determining, which nets in the netlist carry complex symbolic expressions, which comprise more than one symbol;c) replacing said complex expressions with a “crunshed color”, for cutting off said complex symbolic expression from further propagation through the netlist;d) continuing said symbolic simulation including said crunched color information on predetermined nets.

REFERENCES:
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patent: 5493508 (1996-02-01), Dangelo et al.
patent: 6145117 (2000-11-01), Eng
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patent: 6591400 (2003-07-01), Yang
patent: 6745160 (2004-06-01), Ashar et al.
patent: 2004/0107409 (2004-06-01), Melham et al.

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