Method for validating an integrated circuit and related...

Details Method for validating an integrated circuit and related... Method for validating an integrated circuit and related...

2005-05-12

2008-12-09

Chaudry, M. Mujtaba K (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S724000

Reexamination Certificate

active

07464314

ABSTRACT:
A method for converting an integrated circuit into a test circuit for validating functionality of the integrated circuit is disclosed. The integrated circuit is formed on a wafer, and includes a first inner node and a second inner node, wherein the first and second nodes are not floating. The method includes: providing a wire; and utilizing the wire to electrically connect the first inner node to the second inner node, wherein the wire crosses a scribe line of the wafer.

REFERENCES:
patent: 5248936 (1993-09-01), Nakata et al.
patent: 6119255 (2000-09-01), Akram
patent: 7228155 (2007-06-01), Saunders
patent: 2005/0024070 (2005-02-01), Miller
patent: 2005/0070268 (2005-03-01), Hakkinen et al.
patent: 2006/0200715 (2006-09-01), Avery et al.

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