Method for using wafer navigation to reduce testing times of int

Details Method for using wafer navigation to reduce testing times of int Method for using wafer navigation to reduce testing times of int

1997-11-17

2000-11-28

Assouad, Patrick

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

702 81, 700121, G06F 1900

Patent

active

06154714&

ABSTRACT:
A method for testing an integrated circuit wafer is described, wherein the wafer has a first plurality of dice defined thereon, and at least one die has at least one known defect. The method comprises the steps of selecting for testing a first die having a known defect; analyzing connectivity information and defect information relating to the first die, determining, based upon the analysis, a probability of failure for each known defect on the first die, and modifying the sequence of tests performed on the first die so that at least one test which directly relates to a known defect is performed prior to performing tests which are unrelated to a defect.

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