Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2001-03-05
2004-02-10
Moazzami, Nasser G. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S150000, C365S185330, C365S189040, C710S053000, C710S061000
Reexamination Certificate
active
06691205
ABSTRACT:
BACKGROUND OF INVENTION
1. Introduction and Field
The present invention relates to a method for using RAM buffers with multiple accesses in flash-based storage systems. Such RAM buffers enable improved read and write performance of flash-based storage systems, achieved by overlapping read and write operations to the RAM.
2. Prior Art
Using flash memory as a storage media commonly has the 2 following features:
1. Data written to flash generally should be protected by error detection codes and/or error correction codes (EDC/ECC). When the data is read from the flash, EDC/ECC allow the system to determine whether an error is present, and optionally to correct it. The correction can take place in any part of the EDC/ECC-protected data, and therefore should be done in random-access memory, Hence data cannot be sent directly to the host interface (such as SCSI or ATA bus), and should first be read into the RAM. Following this process the EDC/ECC status should be examined. In the case where the EDC/ECC status indicates no error, the data can be passed along. If the EDC/ECC mechanism indicates a correctable error, a corrective action should be taken before passing data further. If the EDC/ECC mechanism indicates an uncorrectable error, this error can optionally be passed to the host interface.
2. A write operation to the flash can also fail. However, this failure can be hidden from the host interface (such as SCSI, or ATA) by writing data onto another location. In order to repeat the write operation, data arriving from the host interface should be placed into the RAM buffer prior to commencing the write operation.
These 2 features inhibit direct data transfer between the host interface and the flash media. Using memory buffer as an intermediary normally takes two consecutive transfer operations: one to the memory and one from the memory. The necessity for these two consecutive data transfers is usually accepted as a necessary evil, and is therefore operative in most flash based storage systems.
There is thus a widely recognized need for, and it would be highly advantageous to have, a system that can enable both operations to and from the memory buffer simultaneously.
The present invention describes a method of performing these two transfer operations simultaneously in a flash-based storage system, thus improving the read and write performances of the system. The system of the present invention is differentiated from known alternative technologies and solutions due to the following factors:
i) The synchronization of host-to-memory and memory-to-flash transfers, and the correct recovery from different flash-related failure operations are complicated to implement, as described in present invention.
ii) Using a RAM buffer as an intermediary for the read and write operations is common, whereas the specific described method of performing these transfer operations simultaneously with a plurality of RAM buffers is unique in flash-based systems, and is thus innovative.
iii) The present invention enables the increase of sustained read and write performance practically twofold.
REFERENCES:
patent: 5359569 (1994-10-01), Fujita et al.
patent: 5412612 (1995-05-01), Oyama
patent: 5438549 (1995-08-01), Levy
patent: 5559952 (1996-09-01), Fujimoto
patent: 5623447 (1997-04-01), Shimoda
patent: 5928370 (1999-07-01), Asnaashari
patent: 6016472 (2000-01-01), Ali
patent: 6418506 (2002-07-01), Pashley et al.
patent: 64-074649 (1989-03-01), None
Friedman Mark M.
M-Systems Flash Disk Pioneers Ltd.
Moazzami Nasser G.
LandOfFree
Method for using RAM buffers with simultaneous accesses in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for using RAM buffers with simultaneous accesses in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for using RAM buffers with simultaneous accesses in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3341833