Method for using partitioned masks to build a chip

Details Method for using partitioned masks to build a chip Method for using partitioned masks to build a chip

2006-02-22

2008-12-23

Lin, Sun J (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07469401

ABSTRACT:
A mask reuse methodology process in which the soft logic is implemented with a generic array type cell structure mask and a custom blocking mask. A method is provided comprising printing a set of component cores onto a die at predetermined locations with a reusable mask set; providing a custom blocking mask that includes opaque regions that positionally correspond with the component cores on the die; superimposing the custom blocking mask with a generic array type cell mask to form superimposed masks; and using the superimposed masks to print generic array type cells onto the die with the exception of the predetermined locations where the set of component cores reside.

REFERENCES:
patent: 5877632 (1999-03-01), Goetting et al.
patent: 6269467 (2001-07-01), Chang et al.
patent: 6383847 (2002-05-01), Ditlow et al.
patent: 6678645 (2004-01-01), Rajsuman et al.
patent: 6976198 (2005-12-01), Vaida
patent: 7176713 (2007-02-01), Madurawe

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