Electrical computers and digital processing systems: virtual mac – Task management or control – Process scheduling
Reexamination Certificate
2003-10-20
2008-11-04
An, Meng-Ai (Department: 2195)
Electrical computers and digital processing systems: virtual mac
Task management or control
Process scheduling
Reexamination Certificate
active
07448038
ABSTRACT:
One aspect of the present invention relates to a method for balancing the load of a parallel processing system having a plurality of parallel processing elements arranged in a loop, wherein each processing element has a local number of tasks associated therewith. The method comprises determining within each processing element a total number of tasks present within the loop, calculating a local mean number of tasks within each processing element, assigning a weight to each of said plurality of processing elements, and calculating a local weighted deviation within each processing element. The method also comprises determining the sum weighted deviations within each processing element for one-half the loop in an anti-clockwise direction and in a clockwise direction, determining clockwise and anti-clockwise transfer parameters within each processing element, and redistributing tasks among the processing elements in response to the clockwise and anti-clockwise transfer parameters.
REFERENCES:
patent: 4386413 (1983-05-01), Vignes et al.
patent: 4633387 (1986-12-01), Hartung et al.
patent: 4992933 (1991-02-01), Taylor
patent: 5109512 (1992-04-01), Bahr et al.
patent: 5241677 (1993-08-01), Naganuma et al.
patent: 5535387 (1996-07-01), Matsouka et al.
patent: 5581773 (1996-12-01), Glover
patent: 5630129 (1997-05-01), Wheat
patent: 5701482 (1997-12-01), Harrison et al.
patent: 5850489 (1998-12-01), Rich
patent: 5892517 (1999-04-01), Rich
patent: 5966528 (1999-10-01), Wilkinson et al.
patent: 6078945 (2000-06-01), Hinsley
patent: 6219776 (2001-04-01), Pechanek et al.
patent: 6279088 (2001-08-01), Elliot et al.
patent: 6292822 (2001-09-01), Hardwick
patent: 6382822 (2002-05-01), Takahashi
patent: 6404439 (2002-06-01), Coulombe et al.
patent: 6421772 (2002-07-01), Maeda et al.
patent: 6430618 (2002-08-01), Karger et al.
patent: 6587938 (2003-07-01), Eilert et al.
patent: 6651082 (2003-11-01), Kawase et al.
patent: 2004/0024874 (2004-02-01), Smith
patent: WO 01/088696 (2001-11-01), None
Daehyun Kim, Mainak Chaudhuri, and Mark Heinrich, Leveraging Cache Coherence in Active Memory Systems, Proceedings of the 16th ACM Int'l Conference on Supercomputing, pp. 2-13, New York City, USA, Jun. 2002.
Mainak Chaudhuri, Daehyun Kim, and Mark Heinrich, Cache Coherence Protocol Design for Active Memory Systems, Proceedings of the 2002 Int'l Conference on Parallel and Distributed Processing Techniques and Applications, pp. 83-89, Las Vegas, USA, Jun. 2002.
Rudolf, Larry; Slivkin-Allalouf, Miriam; UPFAL, Eli; A Simple Load Balancing Scheme for Task Allocation in Parellel Machines; 1991 ACM.
Finnet, Thomas; Calculus; Second Edition 1994, cover page and p. 568.
An Meng-Ai
Jones Day
Micro)n Technology, Inc.
Pencoske Edward L.
Wai Eric C
LandOfFree
Method for using filtering to load balance a loop of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for using filtering to load balance a loop of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for using filtering to load balance a loop of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4036174