Method for using CMP process in a salicide process

Details Method for using CMP process in a salicide process Method for using CMP process in a salicide process

1999-12-01

2001-06-26

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S682000, C438S683000, C438S684000, C438S685000, C438S584000, C257S577000, C257S763000, C257S764000, C257S770000

Reexamination Certificate

active

06251778

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a salicide process. More particularly, it relates to a method for using CMP processes in a salicide process to prevent bridging.
2. Description of the Prior Art
Because of the increasing complexity of electronic devices, the dimensions of MOS devices are shrinking, and the source (drain) resistance is increasing to the level of the channel. In order to lower the source (drain) resistance and keep the shallow junction between the metal and MOS intact, the self-aligned silicide process is widely applied in fabricating VLSI under 0.5 &mgr;m. Such a process is also called a salicide process.
Titanium is a metal which is capable of reacting with oxygen. Under adequate temperature, titanium easily reacts with silicon to form a compound called TiSi
2
with lower resistance by inter-diffusion. Thus, there is good ohmic contact formed between the interface of titanium and silicon. Presently, titanium is the most popular metal used for the salicide process (Co and Pt are alternatives).
FIGS. 1A through 1E
illustrate, in cross section, the conventional salicide process.
Referring to
FIG. 1A
, a basic MOS structure is formed on a semiconductor substrate
10
. The MOS structure includes a defined polysilicon gate
14
, a thin gate oxide
12
, source/drain active regions
16
, spacers
20
formed by chemical vapor deposition (CVD), and field oxide
11
. After cleaning the wafer in a hydrofluoric acid solution to remove all possible contamination, titanium is sputtered, for example by DC magnetron sputtering, to deposit a titanium layer
30
of a thickness between 200 and 1000 Å over the MOS structure, as shown in FIG.
1
B.
Then, the first rapid thermal process, RTP, is performed at between 650 and 800° C. and with a nitrogen gas (N
2
) ambient. During the annealing step, titanium reacts with the polysilicon on the gate
14
and the crystalline silicon of the source/drain active regions and forms TiSi
2
(C49 phase) layers
31
, however, the titanium on the spacer
20
and the field oxide
11
remain intact, as
FIG. 1C
illustrates.
Next, selective etching involving two consecutive wet etchings is used to remove the intact titanium layers. The first etching utilizes a mixture of NH
4
OH, H
2
O
2
, and H
2
O as the etchant, while the second etching utilizes a mixture of H
2
SO
4
and H
2
O
2
as the etchant. The wet etching dissolves the titanium and titanium nitride layer
30
but does not etch the TiSi
2
layers
31
. All the titanium and titanium nitride layers
30
on field oxide
11
and spacer
20
are removed, while the TiSi
2
layers are still left on the polysilicon gate
14
and the source/drain active regions
16
, as
FIG. 1D
illustrates.
Then, the second RTP is performed at about 800-900° C. with a pressure 760 mtorr and with a nitrogen gas (N
2
) ambient. During the annealing step, the TiSi
2
layers
31
of C49 phase are transformed to the TiSi
2
layers
32
of C
54
phase, as
FIG. 1E
illustrates. However, the salicide process according to the prior art has the disadvantages described as follows.
In the titanium salicide process, after HF cleaning, titanium is deposited on wafer in a sputter system. During the first RTP, silicon in the poly gate and source/drain area diffuses into titanium layer and reacts with titanium to form C
49
-TiSi
2
. However, if excess silicon diffuses across the spacer region to form silicide (in this example, TiSi
2
) on top of the spacer, it cannot be removed by selective etching; consequently, the gate and drain/source area become “bridged” together, resulting in a circuit short. As devices become smaller, the spacer width needs to be reduced correspondingly, and thus the distance between the poly gate and source/drain decreases, thereby increasing the possibility of bridging.
In addition, there is a parasitic capacitor between the polysilicon gate and drain/source, wherein the spacer is one dielectric of the parasitic capacitor. While scaling down the devices, the thickness of the spacer is scaled down too, and the parasitic capacitance is increased, such that the operation rate is slowed down due to the large parasitic capacitance.
SUMMARY OF THE INVENTION
Accordingly, an objective of the present invention is to provide a method for using CMP processes in the salicide process to overcome bridging. The bridging between gate and drain/source in the salicide process can be prevented by applying the CMP and the resulting structures according to the present invention.
According to the present invention, a method of fabricating a semiconductor device, includes the steps: (a) providing a semiconductor substrate having a gate electrode and spaced lightly doped source and drain regions, the gate electrode comprising a gate oxide layer and a conducting gate; (b) forming a hard mask layer on the gate electrode; (c) forming spacers on sidewalls of the hard mask layer and the gate electrode, wherein the material used for the spacers is different from the material used for the hard mask layer; (d) implanting ions into the substrate to form highly doped source and drain regions; (e) removing the hard mask layer such that an opening is formed; (f) conformally forming a metal layer on the source and drain regions, the spacers, and the conducting gate; (g) forming an insulating layer on the metal layer and filling the opening, wherein the material of the insulating layer is different from the material of the spacers; (h) polishing to remove an upper portion of the insulating layer, the metal layer and the spacers, whereby the metal layer becomes discontinuous; (i) removing a portion of the metal layer between the spacers and the insulating layer; (j) removing the insulating layer; and(k) converting the metal layer to a silicide layer.
Referring to
FIG. 2I
, an upper end of a spacer is polished off to remove an electrically conductive Ti layer which has been formed thereon. Thereafter, a titanium film and a silicon film are caused to react with each other to produce a TiSi
2
layer of silicide.
Since the conductive layer responsible for the short circuit between the gate electrode and the source-drain region is removed, the bridging between gate and drain/source in the salicide process can be prevented.
According to the present invention, another method of fabricating a semiconductor device, includes the steps: (a) providing a semiconductor substrate having a gate electrode and spaced lightly doped source and drain regions, the gate electrode comprising a gate oxide layer and a conducting gate; (b) forming a hard mask layer on the gate electrode; (c) forming spacers on sidewalls of the hard mask layer and the gate electrode, wherein the material used for the spacers is different from the material used for the hard mask layer; (d) implanting ions into the substrate to form highly doped source and drain regions; (e) removing the hard mask layer such that an opening is formed; (f) conformally forming a metal layer on the source and drain regions, the spacers, and the conducting gate; (g) converting the metal layer to a silicide layer;(h) forming an insulating layer on silicide layer and filling the opening; and(i) polishing to remove an upper portion of the insulating layer, the silicide layer and the spacers, whereby the silicide layer becomes discontinuous.
Referring to
FIG. 3C
, an upper end of a spacer is polished off to remove an electrically conductive TiSi
2
layer which has been formed on the upper end of the spacer.
Since the conductive layer responsible for the short circuit between the gate electrode and the source-drain region is removed, the bridging between gate and drain/source in the salicide process can be prevented.
According to the present invention, another method of fabricating a semiconductor device, includes the steps: (a) providing a semiconductor substrate having a gate electrode and spaced lightly doped source and drain regions, the gate electrode comprising a gate oxide layer and a conducting gate; (b) forming a hard mask layer on the gat

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