Method for using built in self test to characterize input-to-out

Details Method for using built in self test to characterize input-to-out Method for using built in self test to characterize input-to-out

1997-05-27

1998-10-13

Trammell, James P.

Boots, shoes, and leggings

395551, 395550, 395555, 371 211, 371 221, 371 226, G06F 104

Patent

active

058222286

ABSTRACT:
A system and method for using a BIST generator and a BIST compactor to characterize the propagation delay time of a high-speed embedded cores and integrated circuits in general. In one embodiment, an external clock is provided having a positive edge and a negative edge. The BIST generator and test compactor is configured to apply a set of test inputs to the integrated circuit in response to the positive edge, and the BIST compactor is configured to latch a set of outputs from the integrated circuit in response to the negative edge, and determine if the set of outputs represent a valid test result. The validity determination is monitored, and as long as the test result is valid, it is determined that the propagation delay time is less than the time interval between the positive and negative transitions. The propagation delay time can then be measured by reducing the time interval until invalid test results appear. This method provides the means to measure propagation delays of embedded cores more accurately using since tester pulse widths are more accurately measured than tester channel to channel accuracy.

REFERENCES:
patent: 5410547 (1995-04-01), Drain
patent: 5568437 (1996-10-01), Jamal
patent: 5664166 (1997-09-01), Isfeld
patent: 5689690 (1997-11-01), Lesmeister et al.
patent: 5701308 (1997-12-01), Attaway et al.
patent: 5724562 (1998-03-01), Ishiwaki et al.
patent: 5724615 (1998-03-01), Ishii

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