Method for using a mixed-use memory array with different...

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Reexamination Certificate

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C365S158000

Reexamination Certificate

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07486537

ABSTRACT:
A method for using a mixed-use memory array with different data states is disclosed. In one preferred embodiment, a memory array is provided comprising a plurality of memory cells, each memory cell comprising a memory element comprising a switchable resistance material configurable to one of at least three resistivity states. A first set of memory cells uses X resistivity states to represent X respective data states, and a second set of memory cells uses Y resistivity states to represent Y respective data states, wherein X≠Y.

REFERENCES:
patent: 4646266 (1987-02-01), Ovshinsky
patent: 5541869 (1996-07-01), Rose
patent: 5714795 (1998-02-01), Ohmi et al.
patent: 5751012 (1998-05-01), Wolstenholme
patent: 5915167 (1999-06-01), Leedy
patent: 5943264 (1999-08-01), Fournel et al.
patent: 6034882 (2000-03-01), Johnson et al.
patent: 6051851 (2000-04-01), Ohmi et al.
patent: 6055180 (2000-04-01), Gudesen
patent: 6072716 (2000-06-01), Jacobson
patent: 6130835 (2000-10-01), Scheuerlein
patent: 6306718 (2001-10-01), Singh et al.
patent: 6407953 (2002-06-01), Cleeves
patent: 6420215 (2002-07-01), Knall et al.
patent: 6473332 (2002-10-01), Ignatiev
patent: 6478231 (2002-11-01), Taussig
patent: 6483734 (2002-11-01), Sharma et al.
patent: 6483736 (2002-11-01), Johnson et al.
patent: 6545891 (2003-04-01), Tringali et al.
patent: 6552409 (2003-04-01), Taussig et al.
patent: 6567299 (2003-05-01), Kunikiyo et al.
patent: 6584541 (2003-06-01), Friedman et al.
patent: 6618295 (2003-09-01), Scheuerlein
patent: 6646912 (2003-11-01), Hurst et al.
patent: 6694415 (2004-02-01), March et al.
patent: 6711043 (2004-03-01), Friedman et al.
patent: 6731528 (2004-05-01), Hush et al.
patent: 6741495 (2004-05-01), Kunikiyo et al.
patent: 6754098 (2004-06-01), Kunikiyo
patent: 6765813 (2004-07-01), Scheuerlein et al.
patent: 6768661 (2004-07-01), Vyvoda et al.
patent: 6791859 (2004-09-01), Hush et al.
patent: 6791885 (2004-09-01), Casper et al.
patent: 6825489 (2004-11-01), Kozicki
patent: 6834008 (2004-12-01), Rinerson et al.
patent: 6836433 (2004-12-01), Kondo
patent: 6839262 (2005-01-01), Vyvoda et al.
patent: 6839263 (2005-01-01), Fricke et al.
patent: 6856570 (2005-02-01), Fischer
patent: 6858883 (2005-02-01), Fricke et al.
patent: 6868022 (2005-03-01), Scheuerlein et al.
patent: 6879508 (2005-04-01), Tran
patent: 6881623 (2005-04-01), Campbell
patent: 6885604 (2005-04-01), Ott
patent: 6903361 (2005-06-01), Gilton
patent: 6917532 (2005-07-01), Van Brocklin et al.
patent: 6930909 (2005-08-01), Moore et al.
patent: 6947318 (2005-09-01), Fujita
patent: 6950369 (2005-09-01), Kunikiyo et al.
patent: 6952030 (2005-10-01), Herner et al.
patent: 6954385 (2005-10-01), Casper et al.
patent: 6961262 (2005-11-01), Perner
patent: 6996660 (2006-02-01), Moore et al.
patent: 7000063 (2006-02-01), Friedman et al.
patent: 7003619 (2006-02-01), Moore et al.
patent: 7031182 (2006-04-01), Beigel et al.
patent: 7046569 (2006-05-01), Ito et al.
patent: 7062602 (2006-06-01), Moore et al.
patent: 7071008 (2006-07-01), Rinerson et al.
patent: 7095644 (2006-08-01), Chevallier et al.
patent: 7116573 (2006-10-01), Sakamoto et al.
patent: 7132350 (2006-11-01), Yeh et al.
patent: 7161218 (2007-01-01), Bertin et al.
patent: 7176064 (2007-02-01), Herner
patent: 7190611 (2007-03-01), Nguyen et al.
patent: 7205564 (2007-04-01), Kajiyama
patent: 7218550 (2007-05-01), Schwabe et al.
patent: 7224632 (2007-05-01), Moore et al.
patent: 2003/0001230 (2003-01-01), Lowrey
patent: 2003/0047765 (2003-03-01), Campbell
patent: 2003/0115518 (2003-06-01), Kleveland
patent: 2004/0228159 (2004-11-01), Kostylev et al.
patent: 2005/0027928 (2005-02-01), Avraham
patent: 2005/0052915 (2005-03-01), Herner et al.
patent: 2005/0098800 (2005-05-01), Herner et al.
patent: 2005/0121743 (2005-06-01), Herner et al.
patent: 2005/0123837 (2005-06-01), Chen
patent: 2005/0158950 (2005-07-01), Scheuerlein et al.
patent: 2005/0221200 (2005-10-01), Chen
patent: 2005/0226067 (2005-10-01), Herner et al.
patent: 2006/0003586 (2006-01-01), Raghuram et al.
patent: 2006/0047920 (2006-03-01), Moore et al.
patent: 2007/0069276 (2007-03-01), Scheuerlein et al.
patent: 2007/0070690 (2007-03-01), Scheuerlein et al.
patent: 2007/0101131 (2007-05-01), Davtchev et al.
patent: 2007/0164309 (2007-07-01), Kumar et al.
patent: 2008/0017912 (2008-01-01), Kumar et al.
patent: 2008/0023790 (2008-01-01), Scheuerlein et al.
patent: 10 2004 029939 (2006-01-01), None
patent: 0 788 113 (1997-08-01), None
patent: 1450373 (2004-08-01), None
patent: 2004055827 (2004-07-01), None
patent: WO 2005/066969 (2005-07-01), None
patent: WO 2006/121837 (2006-11-01), None
patent: WO 2007/126669 (2007-11-01), None
U.S. Appl. No. 09/877,691; “Method For Re-Directing Data Traffic In A Write-Once Memory Device;” inventors: J. James Tringali, Christopher S. Moore, Roger W. March, James E. Schneider, Derek J. Bosch, And Daniel C. Steere; filing date: Jun. 8, 2001.
U.S. Appl. No. 11/237,167; “Memory Cell Comprising Switchable Semiconductor Memory Element With Trimmable Resistance;” inventors: Kumar et al.; filing date: Sep. 28, 2005.
U.S. Appl. No. 11/395,995; “Nonvolatile Memory Cell Comprising a Diode and a Resistance-Switching Material;” inventors: Herner et al.; filing date: Mar. 31, 2006.
U.S. Appl. No. 11/148,530; “Nonvolatile Memory Cell Operating by Increasing Order in Polycrystalline Semiconductor Material;” inventors: Herner et al.; filing date: Jun. 8, 2006.
U.S. Appl. No. 10/320,470; “An Improved Method for Making High Density Nonvolatile Memory;” inventors: Herner et al.; filing date: Dec. 19, 2002.
U.S. Appl. No. 11/444,936; “Conductive Hard Mask to Protect Patterned Features During Trench Etch;” inventors: Radigan et al.; filing date: May 31, 2006.
U.S. Appl. No. 11/040,356; “A Write-Once Nonvolatile Phase Change Memory Array;” inventor: Scheuerein; filing date: Jan. 29, 2005.
“Multi-Level Cell NAND Flash—The Consumer Choice,” Toshiba America Electronic Corporation, http://www.edn.com/index.asp?layout=articlePrint&articleID-CA503389, Feb. 17, 2005, 5 pages.
“Announcing x4 Technology Breakthrough, msystems Takes the NAND Industry to the Next Level,” msystems, http://www.webwire.com/ViewPressRel—print.asp?ald-14031, May 11, 2006, 3 pages.
U.S. Appl. No. 11/440,899, filed May 24, 2006, titled, “Memory Cell Comprising Nickel-Cobalt Oxide Switching Element,” by Herner.
Alavi et al., A PROM Element Based on Salicide Agglomeration of Poly Fuses in a CMOS Logic Process, IEDM 1997.
Amemiya et al., Electrical Trimming of Heavily Doped Polycrystalline Silicon Resistors, IEEE Transactions Electron Devices, vol. ED-26, No. 11, Nov. 1979.
Babcock, J A., Polysilicon Resistor Trimming for Packaged Integrated Circuits, IEDM 93.
Babcock, J A., Precision Electrical Trimming of Very Low TCR Poly-SiGe Resistors, IEEE Electron Device Letters, vol. 21, No. 6, Jun. 2000.
Das, Soumen et al., A Large-Bias Conduction Model of Polycrystalline Silicon Films, IEEE Transactions on Electron Devices, vol.41, No.4, 524-532, Apr. 1994.
Das, Soumen, et al., Electrical Trimming of Ion-Beam-Sputtered Polysilicon Resistors by High Current Pulses, IEEE Transaction on Electron Devices, vol. 41, No. 8, 1429-1434, Aug. 1994.
Feldbaumer, D W, Pulse Current Trimming of Polysilicon Resistors, IEEE Transactions on Electron Devices, vol. 42, No. 4, 689-696, Apr. 1995.
Feldbaumer, D W. et al., Theory and Application of Polysilicon Resistor Trimming, Solid-State Electronics, vol. 38, No. 11, 1861-1869, Jan. 1995.
Kato, Kotaro et al., A Monolithic 14 Bit D/A Converter Fabricated with a New Trimming Technique (DOT),” IEEE Journal of Solid-State Circuits, vol. SC-19, No. 5, 802-804-806, Oct. 1984.
Kato, Kotaro et al., A Physical Mechanism of Current-Induced Resistance Decrease in Heavily Doped Polysilicon Resistors, IEEE Transaction on Electron Devices, Vo. ED-29, No. 8, 1156-1160, Aug. 1982.
Kato, Kotaro et al., Change in Temperature Coefficient of Resistance of Heavily Doped Polysilico

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