Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-09-20
2005-09-20
Anderson, Matthew D. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S129000, C718S100000
Reexamination Certificate
active
06948034
ABSTRACT:
The present invention has an objective of minimizing deterioration of the processing speed of a Java accelerator device even when stack overflow occurs in a stack memory unit.A first thread presently allocated to a first stack area of a stack memory unit113to which a fourth thread belongs is saved in a virtual stack area of a main storage medium103.Thereafter, the data of the fourth thread as stack data to be switched is copied to the first stack area of the stack memory unit113by the controller unit112(accelerator device101).
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Anderson Matthew D.
Foley & Lardner LLP
NEC Corporation
Patel Hetul
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