Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-06-09
2002-11-12
Wong, Peter (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S025000, C714S030000, C714S031000
Reexamination Certificate
active
06480974
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the use of a bus parking feature for system diagnostics. More specifically, the present invention relates to placing diagnostic information on a bus while the bus is in a parked state.
BACKGROUND OF THE INVENTION
As ASIC devices become more integrated, it has become increasingly difficult to debug new devices, particularly during initial debug testing. Historically, a logic analyzer is used to extract state information from a system to assist in initial debug testing, but due to the large level of integration now used in ASIC design, some of the pertinent state information is buried deep in the chip logic, and is difficult to access with logic analyzers and conventional test equipment.
One solution to this problem is to include dedicated test pins on an ASIC or other device to be tested so that internal state information can be provided on these external pins. However, this solution may be less than optimal because these pins would only be used during debug testing, and rarely (if ever) used again once the device is debugged. Thus, there exists a need for an efficient and cost-effective method for providing internal state information or other diagnostic information for integrated devices such as ASICs.
SUMMARY OF THE INVENTION
In some embodiments, the present invention uses a bus associated with an integrated device to provide diagnostic information about the integrated device during a time where the bus is in a parked or idle state. It is possible to place diagnostic information on the bus in an efficient manner and without disrupting system operation and without the need for additional pins on the integrated device.
In one embodiment of the invention, the invention is a computer comprising (a) a processor, (b) a mezzanine bus, and (c) a chipset attached to the processor and the mezzanine bus. The chipset is configured to operate the mezzanine bus in an active state, operate the mezzanine bus in a parked state, and place diagnostic information on the mezzanine bus during the parked state.
In another embodiment of the present invention, the present invention relates to a method of debugging a device that is connected to a bus that can operate in an active state and a parked state. The method comprises the acts of operating the mezzanine bus in the parked state; placing diagnostic information about the internal states of the device on the bus while the bus is in the parked state; evaluating the diagnostic information; modifying the design of the device in response to the evaluation of the diagnostic information; and disabling the circuitry that places diagnostic information about the internal states of the device on the bus when the bus is in the parked state.
Additional embodiments and features, and the nature of the present invention may be more clearly understood by reference to the following detailed description of the invention, the appended claims, and to the several drawings herein.
REFERENCES:
patent: 4912633 (1990-03-01), Schweizer et al.
patent: 4947357 (1990-08-01), Stewart et al.
patent: 4947395 (1990-08-01), Bullinger et al.
patent: 4953081 (1990-08-01), Feal et al.
patent: 4959772 (1990-09-01), Smith et al.
patent: 4959775 (1990-09-01), Yonekura
patent: 5121487 (1992-06-01), Bechtolsheim
patent: 5133057 (1992-07-01), Ishii et al.
patent: 5133058 (1992-07-01), Jensen
patent: 5151900 (1992-09-01), Snyder et al.
patent: 5175733 (1992-12-01), Nugent
patent: 5198759 (1993-03-01), Ohnesorge
patent: 5276814 (1994-01-01), Bourke et al.
patent: 5280591 (1994-01-01), Garcia et al.
patent: 5317711 (1994-05-01), Bourekas et al.
patent: 5331571 (1994-07-01), Aronoff et al.
patent: 5396602 (1995-03-01), Amini et al.
patent: 5404536 (1995-04-01), Ramakrishnan et al.
patent: 5404538 (1995-04-01), Krappweis, Sr.
patent: 5428623 (1995-06-01), Rahman et al.
patent: 5453992 (1995-09-01), Whetsel
patent: 5467295 (1995-11-01), Young et al.
patent: 5488728 (1996-01-01), Dreyer
patent: 5525971 (1996-06-01), Flynn
patent: 5533205 (1996-07-01), Blackledge, Jr. et al.
patent: 5544311 (1996-08-01), Harenberg et al.
patent: 5546646 (1996-08-01), Williams et al.
patent: 5566300 (1996-10-01), Naoe
patent: 5574730 (1996-11-01), End, III et al.
patent: 5581782 (1996-12-01), Sarangdhar et al.
patent: 5610826 (1997-03-01), Whetsel
patent: 5625785 (1997-04-01), Miura et al.
patent: 5627842 (1997-05-01), Brown et al.
patent: 5633828 (1997-05-01), McClure et al.
patent: 5636166 (1997-06-01), Roohparvar
patent: 5657330 (1997-08-01), Matsumoto
patent: 5701409 (1997-12-01), Gates
patent: 5790811 (1998-08-01), Hewitt
patent: 5822779 (1998-10-01), Intrater et al.
patent: 5838692 (1998-11-01), Tobin
patent: 5838897 (1998-11-01), Bluhm et al.
patent: 5848264 (1998-12-01), Baird et al.
patent: 5907689 (1999-05-01), Tavallaei et al.
PCI to PCI Bridge Architecture Specification.
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Vo Tim
Wong Peter
LandOfFree
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